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arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-26-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2018-03-01 11:05:55 +00:00 committed by Peter Maydell
parent 9869502838
commit b96a54c7e5
3 changed files with 19 additions and 0 deletions
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13
target/arm/helper-a64.c
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@ -828,3 +828,16 @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
}
return float16_to_uint16(a, fpst);
}
/*
* Square Root and Reciprocal square root
*/
float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
{
float_status *s = fpstp;
return float16_sqrt(a, s);
}

1
target/arm/helper-a64.h
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@ -80,3 +80,4 @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
DEF_HELPER_2(sqrt_f16, f16, f16, ptr)

5
target/arm/translate-a64.c
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@ -11388,6 +11388,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */
need_fpst = false;
break;
case 0x7f: /* FSQRT (vector) */
break;
default:
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
@ -11502,6 +11504,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break;
case 0x7f: /* FSQRT */
gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
g_assert_not_reached();
}