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target/riscv: add PRIV_VERSION_LATEST

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All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:

- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()

Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at once when a new priv version is
available.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-05-17 10:57:07 -03:00 committed by Alistair Francis
parent 8c6eeb508a
commit b9a2b98e17
2 changed files with 6 additions and 4 deletions
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8
target/riscv/cpu.c
View File

@ -345,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj)
VM_1_10_SV32 : VM_1_10_SV57); VM_1_10_SV32 : VM_1_10_SV57);
#endif #endif
env->priv_ver = PRIV_VERSION_1_12_0; env->priv_ver = PRIV_VERSION_LATEST;
} }
#if defined(TARGET_RISCV64) #if defined(TARGET_RISCV64)
@ -356,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj)
set_misa(env, MXL_RV64, 0); set_misa(env, MXL_RV64, 0);
riscv_cpu_add_user_properties(obj); riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_1_12_0; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif #endif
@ -462,7 +462,7 @@ static void rv128_base_cpu_init(Object *obj)
set_misa(env, MXL_RV128, 0); set_misa(env, MXL_RV128, 0);
riscv_cpu_add_user_properties(obj); riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_1_12_0; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif #endif
@ -475,7 +475,7 @@ static void rv32_base_cpu_init(Object *obj)
set_misa(env, MXL_RV32, 0); set_misa(env, MXL_RV32, 0);
riscv_cpu_add_user_properties(obj); riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_1_12_0; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif #endif

2
target/riscv/cpu.h
View File

@ -61,6 +61,8 @@ enum {
PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0, PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0, PRIV_VERSION_1_12_0,
PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
}; };
#define VEXT_VERSION_1_00_0 0x00010000 #define VEXT_VERSION_1_00_0 0x00010000