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target-mips: fix 34Kf configuration for DSP ASE

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34Kf core does support DSP ASE.
CP0_Config3 configuration for 34Kf and description are wrong.

Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Yongbok Kim 2013-08-02 10:33:43 +01:00 committed by Aurelien Jarno
parent 2ddc463725
commit b9ac5d923b
1 changed files with 3 additions and 4 deletions
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7
target-mips/translate_init.c
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@ -274,14 +274,13 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA), (1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT), .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
(1 << CP0C3_DSPP),
.CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0, .CP0_LLAddr_shift = 0,
.SYNCI_Step = 32, .SYNCI_Step = 32,
.CCRes = 2, .CCRes = 2,
/* No DSP implemented. */ .CP0_Status_rw_bitmask = 0x3778FF1F,
.CP0_Status_rw_bitmask = 0x3678FF1F,
/* No DSP implemented. */
.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
(0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |