openpic: update to proper memory api
The openpic code was still using the old mmio memory api. Convert it to be a generic memory api user and clean up some code that becomes redundant that way. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
cdbb912a6f
commit
b9b2aaa3c6
138
hw/openpic.c
138
hw/openpic.c
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@ -461,7 +461,8 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
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opp->src[n_IRQ].ipvp);
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}
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static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
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static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *opp = opaque;
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IRQ_dst_t *dst;
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@ -527,7 +528,7 @@ static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
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}
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}
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static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
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static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *opp = opaque;
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uint32_t retval;
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@ -584,7 +585,8 @@ static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
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return retval;
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}
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static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
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static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *opp = opaque;
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int idx;
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@ -615,7 +617,7 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
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}
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}
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static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
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static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *opp = opaque;
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uint32_t retval;
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@ -648,7 +650,8 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
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return retval;
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}
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static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
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static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *opp = opaque;
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int idx;
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@ -667,7 +670,7 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
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}
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}
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static uint32_t openpic_src_read (void *opaque, uint32_t addr)
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static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
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{
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openpic_t *opp = opaque;
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uint32_t retval;
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@ -749,7 +752,8 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
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}
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}
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static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
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static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
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}
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@ -833,96 +837,63 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
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return retval;
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}
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static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
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static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
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{
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return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
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}
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static void openpic_buggy_write (void *opaque,
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hwaddr addr, uint32_t val)
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{
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printf("Invalid OPENPIC write access !\n");
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}
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static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
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{
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printf("Invalid OPENPIC read access !\n");
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return -1;
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}
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static void openpic_writel (void *opaque,
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hwaddr addr, uint32_t val)
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static void openpic_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *opp = opaque;
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addr &= 0x3FFFF;
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DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
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if (addr < 0x1100) {
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/* Global registers */
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openpic_gbl_write(opp, addr, val);
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openpic_gbl_write(opp, addr, val, len);
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} else if (addr < 0x10000) {
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/* Timers registers */
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openpic_timer_write(opp, addr, val);
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openpic_timer_write(opp, addr, val, len);
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} else if (addr < 0x20000) {
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/* Source registers */
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openpic_src_write(opp, addr, val);
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openpic_src_write(opp, addr, val, len);
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} else {
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/* CPU registers */
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openpic_cpu_write(opp, addr, val);
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openpic_cpu_write(opp, addr, val, len);
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}
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}
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static uint32_t openpic_readl (void *opaque,hwaddr addr)
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static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *opp = opaque;
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uint32_t retval;
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addr &= 0x3FFFF;
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DPRINTF("%s: offset %08x\n", __func__, (int)addr);
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if (addr < 0x1100) {
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/* Global registers */
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retval = openpic_gbl_read(opp, addr);
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retval = openpic_gbl_read(opp, addr, len);
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} else if (addr < 0x10000) {
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/* Timers registers */
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retval = openpic_timer_read(opp, addr);
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retval = openpic_timer_read(opp, addr, len);
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} else if (addr < 0x20000) {
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/* Source registers */
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retval = openpic_src_read(opp, addr);
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retval = openpic_src_read(opp, addr, len);
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} else {
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/* CPU registers */
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retval = openpic_cpu_read(opp, addr);
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retval = openpic_cpu_read(opp, addr, len);
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}
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return retval;
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}
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static uint64_t openpic_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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openpic_t *opp = opaque;
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switch (size) {
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case 4: return openpic_readl(opp, addr);
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default: return openpic_buggy_read(opp, addr);
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}
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}
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static void openpic_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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openpic_t *opp = opaque;
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switch (size) {
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case 4: return openpic_writel(opp, addr, data);
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default: return openpic_buggy_write(opp, addr, data);
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}
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}
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static const MemoryRegionOps openpic_ops = {
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.read = openpic_read,
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.write = openpic_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
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@ -1131,7 +1102,8 @@ static void mpic_reset (void *opaque)
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mpp->glbc = 0x00000000;
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}
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static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
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static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned len)
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{
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openpic_t *mpp = opaque;
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int idx, cpu;
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@ -1139,7 +1111,6 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
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DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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return;
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addr &= 0xFFFF;
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cpu = addr >> 12;
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idx = (addr >> 6) & 0x3;
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switch (addr & 0x30) {
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@ -1164,7 +1135,7 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
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}
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}
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static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
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static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len)
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{
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openpic_t *mpp = opaque;
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uint32_t retval;
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@ -1174,7 +1145,6 @@ static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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return retval;
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addr &= 0xFFFF;
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cpu = addr >> 12;
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idx = (addr >> 6) & 0x3;
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switch (addr & 0x30) {
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@ -1242,45 +1212,33 @@ static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len)
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}
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static const MemoryRegionOps mpic_glb_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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openpic_gbl_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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openpic_gbl_read,
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},
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},
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.write = openpic_gbl_write,
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.read = openpic_gbl_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps mpic_tmr_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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mpic_timer_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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mpic_timer_read,
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},
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},
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.write = mpic_timer_write,
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.read = mpic_timer_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps mpic_cpu_ops = {
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.old_mmio = {
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.write = { openpic_buggy_write,
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openpic_buggy_write,
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openpic_cpu_write,
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},
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.read = { openpic_buggy_read,
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openpic_buggy_read,
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openpic_cpu_read,
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},
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},
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.write = openpic_cpu_write,
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.read = openpic_cpu_read,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps mpic_irq_ops = {
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