target-alpha: Disassemble EV6 PALcode instructions.
The QEMU emulation PALcode will use EV6 PALcode insns regardless of the "real" cpu instruction set being emulated. Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -238,10 +238,6 @@ extern const unsigned alpha_num_operands;
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#define AXP_REG_SP 30
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#define AXP_REG_ZERO 31
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#define bfd_mach_alpha_ev4 0x10
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#define bfd_mach_alpha_ev5 0x20
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#define bfd_mach_alpha_ev6 0x30
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enum bfd_reloc_code_real {
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BFD_RELOC_23_PCREL_S2,
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BFD_RELOC_ALPHA_HINT
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@ -184,6 +184,9 @@ enum bfd_architecture
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#define bfd_mach_sh5 0x50
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bfd_arch_alpha, /* Dec Alpha */
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#define bfd_mach_alpha 1
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#define bfd_mach_alpha_ev4 0x10
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#define bfd_mach_alpha_ev5 0x20
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#define bfd_mach_alpha_ev6 0x30
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bfd_arch_arm, /* Advanced Risc Machines ARM */
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#define bfd_mach_arm_unknown 0
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#define bfd_mach_arm_2 1
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2
disas.c
2
disas.c
@ -205,7 +205,7 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
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disasm_info.mach = bfd_mach_sh4;
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print_insn = print_insn_sh;
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#elif defined(TARGET_ALPHA)
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disasm_info.mach = bfd_mach_alpha;
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disasm_info.mach = bfd_mach_alpha_ev6;
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print_insn = print_insn_alpha;
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#elif defined(TARGET_CRIS)
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if (flags != 32) {
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