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target-alpha: Disassemble EV6 PALcode instructions.

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The QEMU emulation PALcode will use EV6 PALcode insns regardless
of the "real" cpu instruction set being emulated.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2011-04-10 10:31:20 -07:00 committed by Richard Henderson
parent 8d6df264f1
commit b9bec751c8
3 changed files with 4 additions and 5 deletions
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4
alpha-dis.c
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@ -238,10 +238,6 @@ extern const unsigned alpha_num_operands;
#define AXP_REG_SP 30 #define AXP_REG_SP 30
#define AXP_REG_ZERO 31 #define AXP_REG_ZERO 31
#define bfd_mach_alpha_ev4 0x10
#define bfd_mach_alpha_ev5 0x20
#define bfd_mach_alpha_ev6 0x30
enum bfd_reloc_code_real { enum bfd_reloc_code_real {
BFD_RELOC_23_PCREL_S2, BFD_RELOC_23_PCREL_S2,
BFD_RELOC_ALPHA_HINT BFD_RELOC_ALPHA_HINT

3
dis-asm.h
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@ -184,6 +184,9 @@ enum bfd_architecture
#define bfd_mach_sh5 0x50 #define bfd_mach_sh5 0x50
bfd_arch_alpha, /* Dec Alpha */ bfd_arch_alpha, /* Dec Alpha */
#define bfd_mach_alpha 1 #define bfd_mach_alpha 1
#define bfd_mach_alpha_ev4 0x10
#define bfd_mach_alpha_ev5 0x20
#define bfd_mach_alpha_ev6 0x30
bfd_arch_arm, /* Advanced Risc Machines ARM */ bfd_arch_arm, /* Advanced Risc Machines ARM */
#define bfd_mach_arm_unknown 0 #define bfd_mach_arm_unknown 0
#define bfd_mach_arm_2 1 #define bfd_mach_arm_2 1

2
disas.c
View File

@ -205,7 +205,7 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
disasm_info.mach = bfd_mach_sh4; disasm_info.mach = bfd_mach_sh4;
print_insn = print_insn_sh; print_insn = print_insn_sh;
#elif defined(TARGET_ALPHA) #elif defined(TARGET_ALPHA)
disasm_info.mach = bfd_mach_alpha; disasm_info.mach = bfd_mach_alpha_ev6;
print_insn = print_insn_alpha; print_insn = print_insn_alpha;
#elif defined(TARGET_CRIS) #elif defined(TARGET_CRIS)
if (flags != 32) { if (flags != 32) {