Merge remote-tracking branch 'pm-arm/for-upstream' into pm
This commit is contained in:
Edgar E. Iglesias
commit
b9c6cbff76
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@ -374,6 +374,7 @@ enum arm_features {
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ARM_FEATURE_V4T,
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ARM_FEATURE_V5,
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ARM_FEATURE_STRONGARM,
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ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -420,6 +421,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
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#define ARM_CPUID_PXA270_C5 0x69054117
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#define ARM_CPUID_ARM1136 0x4117b363
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#define ARM_CPUID_ARM1136_R2 0x4107b362
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#define ARM_CPUID_ARM1176 0x410fb767
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#define ARM_CPUID_ARM11MPCORE 0x410fb022
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#define ARM_CPUID_CORTEXA8 0x410fc080
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#define ARM_CPUID_CORTEXA9 0x410fc090
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@ -35,6 +35,12 @@ static uint32_t arm1136_cp15_c0_c1[8] =
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static uint32_t arm1136_cp15_c0_c2[8] =
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{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
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static uint32_t arm1176_cp15_c0_c1[8] =
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{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
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static uint32_t arm1176_cp15_c0_c2[8] =
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{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
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static uint32_t cpu_arm_find_by_name(const char *name);
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static inline void set_feature(CPUARMState *env, int feature)
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@ -70,13 +76,24 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_ARM1136_R2:
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case ARM_CPUID_ARM1136:
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/* This is the 1136 r1, which is a v6K core */
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set_feature(env, ARM_FEATURE_V6K);
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/* Fall through */
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case ARM_CPUID_ARM1136_R2:
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/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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*/
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set_feature(env, ARM_FEATURE_V4T);
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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/* These ID register values are correct for 1136 but may be wrong
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* for 1136_r2 (in particular r0p2 does not actually implement most
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* of the ID registers).
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*/
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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@ -85,6 +102,22 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM1176:
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set_feature(env, ARM_FEATURE_V4T);
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_V6K);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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set_feature(env, ARM_FEATURE_VAPA);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM11MPCORE:
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set_feature(env, ARM_FEATURE_V4T);
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set_feature(env, ARM_FEATURE_V5);
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@ -92,6 +125,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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set_feature(env, ARM_FEATURE_V6K);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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set_feature(env, ARM_FEATURE_VAPA);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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@ -222,6 +256,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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cpu_abort(env, "Bad CPU ID: %x\n", id);
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break;
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}
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA);
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}
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}
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void cpu_reset(CPUARMState *env)
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@ -380,6 +419,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
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{ ARM_CPUID_ARM1026, "arm1026"},
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{ ARM_CPUID_ARM1136, "arm1136"},
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{ ARM_CPUID_ARM1136_R2, "arm1136-r2"},
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{ ARM_CPUID_ARM1176, "arm1176"},
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{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
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{ ARM_CPUID_CORTEXM3, "cortex-m3"},
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{ ARM_CPUID_CORTEXA8, "cortex-a8"},
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@ -948,7 +988,7 @@ static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
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case 6:
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return prot_ro;
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case 7:
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if (!arm_feature (env, ARM_FEATURE_V7))
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if (!arm_feature (env, ARM_FEATURE_V6K))
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return 0;
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return prot_ro;
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default:
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@ -1502,7 +1542,7 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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goto bad_reg;
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}
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/* No cache, so nothing to do except VA->PA translations. */
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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if (arm_feature(env, ARM_FEATURE_VAPA)) {
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switch (crm) {
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case 4:
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if (arm_feature(env, ARM_FEATURE_V7)) {
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@ -1848,6 +1888,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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return 1;
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case ARM_CPUID_ARM1136:
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case ARM_CPUID_ARM1136_R2:
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case ARM_CPUID_ARM1176:
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return 7;
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case ARM_CPUID_ARM11MPCORE:
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return 1;
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@ -2498,12 +2498,6 @@ static int cp15_user_ok(CPUState *env, uint32_t insn)
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if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
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return 1;
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}
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if (cpn == 7) {
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/* ISB, DSB, DMB. */
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if ((cpm == 5 && op == 4)
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|| (cpm == 10 && (op == 4 || op == 5)))
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return 1;
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}
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return 0;
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}
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@ -2579,39 +2573,60 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
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/* cdp */
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return 1;
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}
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if (IS_USER(s) && !cp15_user_ok(env, insn)) {
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return 1;
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}
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/* Pre-v7 versions of the architecture implemented WFI via coprocessor
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* instructions rather than a separate instruction.
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/* We special case a number of cp15 instructions which were used
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* for things which are real instructions in ARMv7. This allows
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* them to work in linux-user mode which doesn't provide functional
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* get_cp15/set_cp15 helpers, and is more efficient anyway.
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*/
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if ((insn & 0x0fff0fff) == 0x0e070f90) {
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switch ((insn & 0x0fff0fff)) {
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case 0x0e070f90:
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/* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
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* In v7, this must NOP.
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*/
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if (IS_USER(s)) {
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return 1;
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}
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if (!arm_feature(env, ARM_FEATURE_V7)) {
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/* Wait for interrupt. */
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gen_set_pc_im(s->pc);
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s->is_jmp = DISAS_WFI;
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}
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return 0;
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}
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if ((insn & 0x0fff0fff) == 0x0e070f58) {
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case 0x0e070f58:
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/* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
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* so this is slightly over-broad.
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*/
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if (!arm_feature(env, ARM_FEATURE_V6)) {
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if (!IS_USER(s) && !arm_feature(env, ARM_FEATURE_V6)) {
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/* Wait for interrupt. */
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gen_set_pc_im(s->pc);
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s->is_jmp = DISAS_WFI;
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return 0;
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}
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/* Otherwise fall through to handle via helper function.
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/* Otherwise continue to handle via helper function.
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* In particular, on v7 and some v6 cores this is one of
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* the VA-PA registers.
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*/
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break;
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case 0x0e070f3d:
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/* 0,c7,c13,1: prefetch-by-MVA in v6, NOP in v7 */
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if (arm_feature(env, ARM_FEATURE_V6)) {
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return IS_USER(s) ? 1 : 0;
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}
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break;
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case 0x0e070f95: /* 0,c7,c5,4 : ISB */
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case 0x0e070f9a: /* 0,c7,c10,4: DSB */
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case 0x0e070fba: /* 0,c7,c10,5: DMB */
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/* Barriers in both v6 and v7 */
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if (arm_feature(env, ARM_FEATURE_V6)) {
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return 0;
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}
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break;
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default:
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break;
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}
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if (IS_USER(s) && !cp15_user_ok(env, insn)) {
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return 1;
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}
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rd = (insn >> 12) & 0xf;
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@ -3056,6 +3071,17 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
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/* Source and destination the same. */
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gen_mov_F0_vreg(dp, rd);
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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/* VCVTB, VCVTT: only present with the halfprec extension,
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* UNPREDICTABLE if bit 8 is set (we choose to UNDEF)
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*/
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if (dp || !arm_feature(env, ARM_FEATURE_VFP_FP16)) {
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return 1;
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}
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/* Otherwise fall through */
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default:
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/* One source operand. */
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gen_mov_F0_vreg(dp, rm);
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@ -3152,24 +3178,18 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
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gen_vfp_sqrt(dp);
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break;
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case 4: /* vcvtb.f32.f16 */
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if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
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return 1;
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tmp = gen_vfp_mrs();
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tcg_gen_ext16u_i32(tmp, tmp);
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gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
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tcg_temp_free_i32(tmp);
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break;
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case 5: /* vcvtt.f32.f16 */
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if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
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return 1;
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tmp = gen_vfp_mrs();
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tcg_gen_shri_i32(tmp, tmp, 16);
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gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
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tcg_temp_free_i32(tmp);
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break;
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case 6: /* vcvtb.f16.f32 */
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if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
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return 1;
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tmp = tcg_temp_new_i32();
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gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
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gen_mov_F0_vreg(0, rd);
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@ -3180,8 +3200,6 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
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gen_vfp_msr(tmp);
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break;
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case 7: /* vcvtt.f16.f32 */
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if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
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return 1;
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tmp = tcg_temp_new_i32();
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gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
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tcg_gen_shli_i32(tmp, tmp, 16);
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@ -3270,12 +3288,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
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gen_vfp_toul(dp, 32 - rm, 0);
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break;
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default: /* undefined */
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printf ("rn:%d\n", rn);
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return 1;
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}
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break;
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default: /* undefined */
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printf ("op:%d\n", op);
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return 1;
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}
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@ -3382,17 +3398,18 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
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VFP_DREG_D(rd, insn);
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else
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rd = VFP_SREG_D(insn);
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if (s->thumb && rn == 15) {
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, rn);
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}
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if ((insn & 0x01200000) == 0x01000000) {
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/* Single load/store */
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offset = (insn & 0xff) << 2;
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if ((insn & (1 << 23)) == 0)
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offset = -offset;
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if (s->thumb && rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, rn);
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}
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tcg_gen_addi_i32(addr, addr, offset);
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if (insn & (1 << 20)) {
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gen_vfp_ld(s, dp, addr);
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@ -3404,11 +3421,34 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
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tcg_temp_free_i32(addr);
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} else {
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/* load/store multiple */
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int w = insn & (1 << 21);
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if (dp)
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n = (insn >> 1) & 0x7f;
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else
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n = insn & 0xff;
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if (w && !(((insn >> 23) ^ (insn >> 24)) & 1)) {
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/* P == U , W == 1 => UNDEF */
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return 1;
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}
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if (n == 0 || (rd + n) > 32 || (dp && n > 16)) {
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/* UNPREDICTABLE cases for bad immediates: we choose to
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* UNDEF to avoid generating huge numbers of TCG ops
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*/
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return 1;
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}
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if (rn == 15 && w) {
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/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
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return 1;
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}
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if (s->thumb && rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, rn);
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}
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if (insn & (1 << 24)) /* pre-decrement */
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tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
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@ -3428,7 +3468,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
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}
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tcg_gen_addi_i32(addr, addr, offset);
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}
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if (insn & (1 << 21)) {
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if (w) {
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/* writeback */
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if (insn & (1 << 24))
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offset = -offset * n;
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@ -6330,8 +6370,6 @@ static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
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return 0;
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}
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}
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fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
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op1, crn, crm, op2);
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return 1;
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}
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@ -6363,8 +6401,6 @@ static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
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return 0;
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}
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}
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fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
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op1, crn, crm, op2);
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return 1;
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||||
}
|
||||
|
||||
|
|
|
|||
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