Hexagon (target/hexagon) put writes to USR into temp until commit
Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead of hex_gpr[HEX_REG_USR]. Then, we need code to mark the instructions that can set implicitly set USR - Macros added to hex_common.py - A_FPOP added in translate.c Test case added in tests/tcg/hexagon/overflow.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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@ -64,6 +64,7 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
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DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
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DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
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DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
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DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
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DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
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DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
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@ -73,6 +73,8 @@ def calculate_attribs():
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add_qemu_macro_attrib('fWRITE_P1', 'A_WRITES_PRED_REG')
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add_qemu_macro_attrib('fWRITE_P2', 'A_WRITES_PRED_REG')
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add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
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add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
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add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
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# Recurse down macros, find attributes from sub-macros
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macroValues = list(macros.values())
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@ -62,7 +62,7 @@
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reg_field_info[FIELD].offset)
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#define SET_USR_FIELD(FIELD, VAL) \
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fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
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fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
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reg_field_info[FIELD].offset, (VAL))
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#endif
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@ -204,7 +204,12 @@ static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
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int attrib, int rnum)
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{
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if (GET_ATTRIB(insn->opcode, attrib)) {
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bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC);
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/*
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* USR is used to set overflow and FP exceptions,
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* so treat it as conditional
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*/
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bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC) ||
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rnum == HEX_REG_USR;
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if (is_predicated && !is_preloaded(ctx, rnum)) {
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tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]);
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}
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@ -230,6 +235,8 @@ static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_USR, HEX_REG_USR);
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mark_implicit_reg_write(ctx, insn, A_FPOP, HEX_REG_USR);
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}
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static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
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@ -40,5 +40,6 @@ HEX_TESTS += load_unpack
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HEX_TESTS += load_align
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HEX_TESTS += atomics
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HEX_TESTS += fpstuff
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HEX_TESTS += overflow
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TESTS += $(HEX_TESTS)
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@ -0,0 +1,107 @@
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/*
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* Copyright(c) 2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <fcntl.h>
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#include <setjmp.h>
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#include <signal.h>
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int err;
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static void __check(const char *filename, int line, int x, int expect)
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{
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if (x != expect) {
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printf("ERROR %s:%d - %d != %d\n",
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filename, line, x, expect);
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err++;
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}
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}
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#define check(x, expect) __check(__FILE__, __LINE__, (x), (expect))
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static int satub(int src, int *p, int *ovf_result)
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{
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int result;
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int usr;
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/*
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* This instruction can set bit 0 (OVF/overflow) in usr
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* Clear the bit first, then return that bit to the caller
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*
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* We also store the src into *p in the same packet, so we
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* can ensure the overflow doesn't get set when an exception
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* is generated.
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*/
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asm volatile("r2 = usr\n\t"
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"r2 = clrbit(r2, #0)\n\t" /* clear overflow bit */
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"usr = r2\n\t"
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"{\n\t"
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" %0 = satub(%2)\n\t"
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" memw(%3) = %2\n\t"
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"}\n\t"
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"%1 = usr\n\t"
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: "=r"(result), "=r"(usr)
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: "r"(src), "r"(p)
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: "r2", "usr", "memory");
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*ovf_result = (usr & 1);
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return result;
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}
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int read_usr_overflow(void)
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{
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int result;
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asm volatile("%0 = usr\n\t" : "=r"(result));
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return result & 1;
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}
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jmp_buf jmp_env;
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int usr_overflow;
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static void sig_segv(int sig, siginfo_t *info, void *puc)
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{
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usr_overflow = read_usr_overflow();
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longjmp(jmp_env, 1);
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}
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int main()
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{
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struct sigaction act;
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int ovf;
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/* SIGSEGV test */
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act.sa_sigaction = sig_segv;
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sigemptyset(&act.sa_mask);
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act.sa_flags = SA_SIGINFO;
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sigaction(SIGSEGV, &act, NULL);
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if (setjmp(jmp_env) == 0) {
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satub(300, 0, &ovf);
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}
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act.sa_handler = SIG_DFL;
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sigemptyset(&act.sa_mask);
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act.sa_flags = 0;
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check(usr_overflow, 0);
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puts(err ? "FAIL" : "PASS");
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return err ? EXIT_FAILURE : EXIT_SUCCESS;
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}
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