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target-arm queue: 

* Fixes for various bugs in SVE instructions
  * Add model of Freescale i.MX6 UltraLite 14x14 EVK Board
  * hw/arm: make bitbanded IO optional on ARMv7-M
  * Add model of Cortex-M0 CPU
  * Add support for loading Intel HEX files to the generic loader
  * imx_spi: Unset XCH when TX FIFO becomes empty
  * aspeed_sdmc: fix various bugs
  * Fix bugs in Arm FP16 instruction support
  * Fix aa64 FCADD and FCMLA decode
  * softfloat: Fix missing inexact for floating-point add
  * hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180816' into staging

target-arm queue:
 * Fixes for various bugs in SVE instructions
 * Add model of Freescale i.MX6 UltraLite 14x14 EVK Board
 * hw/arm: make bitbanded IO optional on ARMv7-M
 * Add model of Cortex-M0 CPU
 * Add support for loading Intel HEX files to the generic loader
 * imx_spi: Unset XCH when TX FIFO becomes empty
 * aspeed_sdmc: fix various bugs
 * Fix bugs in Arm FP16 instruction support
 * Fix aa64 FCADD and FCMLA decode
 * softfloat: Fix missing inexact for floating-point add
 * hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()

# gpg: Signature made Thu 16 Aug 2018 14:33:41 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180816: (30 commits)
  hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
  softfloat: Fix missing inexact for floating-point add
  target/arm: Fix aa64 FCADD and FCMLA decode
  target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
  target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
  target/arm: Ignore float_flag_input_denormal from fp_status_f16
  target/arm: Adjust FPCR_MASK for FZ16
  aspeed: add a max_ram_size property to the memory controller
  aspeed_sdmc: Handle ECC training
  aspeed_sdmc: Init status always idle
  aspeed_sdmc: Set 'cache initial sequence' always true
  aspeed_sdmc: Fix saved values
  aspeed_sdmc: Extend number of valid registers
  imx_spi: Unset XCH when TX FIFO becomes empty
  Add QTest testcase for the Intel Hexadecimal
  loader: Implement .hex file loader
  loader: add rom transaction API
  loader: extract rom_free() function
  target/arm: add "cortex-m0" CPU model
  hw/arm: make bitbanded IO optional on ARMv7-M
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-08-16 14:35:50 +01:00
parent c542a9f979 fcf13ca556
commit bb16c0412a
38 changed files with 2863 additions and 126 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -1323,6 +1323,12 @@ F: hw/core/generic-loader.c
F: include/hw/core/generic-loader.h
F: docs/generic-loader.txt
Intel Hexadecimal Object File Loader
M: Su Hang <suhang16@mails.ucas.ac.cn>
S: Maintained
F: tests/hexloader-test.c
F: tests/hex-loader-check-data/test.hex
CHRP NVRAM
M: Thomas Huth <thuth@redhat.com>
S: Maintained

4
configure vendored
View File

@ -7382,6 +7382,10 @@ for test_file in $(find $source_path/tests/acpi-test-data -type f)
do
FILES="$FILES tests/acpi-test-data$(echo $test_file | sed -e 's/.*acpi-test-data//')"
done
for test_file in $(find $source_path/tests/hex-loader-check-data -type f)
do
FILES="$FILES tests/hex-loader-check-data$(echo $test_file | sed -e 's/.*hex-loader-check-data//')"
done
mkdir -p $DIRS
for f in $FILES ; do
if [ -e "$source_path/$f" ] && [ "$pwd_is_source_path" != "y" ]; then

1
default-configs/arm-softmmu.mak
View File

@ -133,6 +133,7 @@ CONFIG_FSL_IMX6=y
CONFIG_FSL_IMX31=y
CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_IMX_I2C=y

2
fpu/softfloat.c
View File

@ -701,7 +701,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract,
}
a.frac += b.frac;
if (a.frac & DECOMPOSED_OVERFLOW_BIT) {
a.frac >>= 1;
shift64RightJamming(a.frac, 1, &a.frac);
a.exp += 1;
}
return a;

1
hw/arm/Makefile.objs
View File

@ -36,3 +36,4 @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
obj-$(CONFIG_IOTKIT) += iotkit.o
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o

37
hw/arm/armv7m.c
View File

@ -211,25 +211,27 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, 0xe000e000,
sysbus_mmio_get_region(sbd, 0));
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
Object *obj = OBJECT(&s->bitband[i]);
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
if (s->enable_bitband) {
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
Object *obj = OBJECT(&s->bitband[i]);
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
object_property_set_int(obj, bitband_input_addr[i], "base", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
object_property_set_link(obj, OBJECT(s->board_memory),
"source-memory", &error_abort);
object_property_set_bool(obj, true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
object_property_set_int(obj, bitband_input_addr[i], "base", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
object_property_set_link(obj, OBJECT(s->board_memory),
"source-memory", &error_abort);
object_property_set_bool(obj, true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, bitband_output_addr[i],
sysbus_mmio_get_region(sbd, 0));
memory_region_add_subregion(&s->container, bitband_output_addr[i],
sysbus_mmio_get_region(sbd, 0));
}
}
}
@ -239,6 +241,7 @@ static Property armv7m_properties[] = {
MemoryRegion *),
DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
DEFINE_PROP_END_OF_LIST(),
};

31
hw/arm/aspeed.c
View File

@ -31,6 +31,7 @@ static struct arm_boot_info aspeed_board_binfo = {
typedef struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram;
MemoryRegion max_ram;
} AspeedBoardState;
typedef struct AspeedBoardConfig {
@ -127,6 +128,27 @@ static const AspeedBoardConfig aspeed_boards[] = {
},
};
/*
* The max ram region is for firmwares that scan the address space
* with load/store to guess how much RAM the SoC has.
*/
static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
{
return 0;
}
static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
/* Discard writes */
}
static const MemoryRegionOps max_ram_ops = {
.read = max_ram_read,
.write = max_ram_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define FIRMWARE_ADDR 0x0
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
@ -187,6 +209,7 @@ static void aspeed_board_init(MachineState *machine,
AspeedBoardState *bmc;
AspeedSoCClass *sc;
DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
ram_addr_t max_ram_size;
bmc = g_new0(AspeedBoardState, 1);
object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
@ -226,6 +249,14 @@ static void aspeed_board_init(MachineState *machine,
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
&error_abort);
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
"max_ram", max_ram_size - ram_size);
memory_region_add_subregion(get_system_memory(),
sc->info->sdram_base + ram_size,
&bmc->max_ram);
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);

2
hw/arm/aspeed_soc.c
View File

@ -155,6 +155,8 @@ static void aspeed_soc_init(Object *obj)
sc->info->silicon_rev);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size", &error_abort);
object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
"max-ram-size", &error_abort);
for (i = 0; i < sc->info->wdts_num; i++) {
object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);

617
hw/arm/fsl-imx6ul.c Normal file
View File

@ -0,0 +1,617 @@
/*
* Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
*
* i.MX6UL SOC emulation.
*
* Based on hw/arm/fsl-imx7.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/misc/unimp.h"
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#define NAME_SIZE 20
static void fsl_imx6ul_init(Object *obj)
{
FslIMX6ULState *s = FSL_IMX6UL(obj);
char name[NAME_SIZE];
int i;
for (i = 0; i < MIN(smp_cpus, FSL_IMX6UL_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
"cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
}
/*
* A7MPCORE
*/
sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
TYPE_A15MPCORE_PRIV);
/*
* CCM
*/
sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
/*
* SRC
*/
sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
/*
* GPCv2
*/
sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
TYPE_IMX_GPCV2);
/*
* SNVS
*/
sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
TYPE_IMX7_SNVS);
/*
* GPR
*/
sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
TYPE_IMX7_GPR);
/*
* GPIOs 1 to 5
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
snprintf(name, NAME_SIZE, "gpio%d", i);
sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
TYPE_IMX_GPIO);
}
/*
* GPT 1, 2
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
snprintf(name, NAME_SIZE, "gpt%d", i);
sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
TYPE_IMX7_GPT);
}
/*
* EPIT 1, 2
*/
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
snprintf(name, NAME_SIZE, "epit%d", i + 1);
sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
TYPE_IMX_EPIT);
}
/*
* eCSPI
*/
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
TYPE_IMX_SPI);
}
/*
* I2C
*/
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
TYPE_IMX_I2C);
}
/*
* UART
*/
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
snprintf(name, NAME_SIZE, "uart%d", i);
sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
TYPE_IMX_SERIAL);
}
/*
* Ethernet
*/
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
snprintf(name, NAME_SIZE, "eth%d", i);
sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
TYPE_IMX_ENET);
}
/*
* SDHCI
*/
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
snprintf(name, NAME_SIZE, "usdhc%d", i);
sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
TYPE_IMX_USDHC);
}
/*
* Watchdog
*/
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
snprintf(name, NAME_SIZE, "wdt%d", i);
sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
TYPE_IMX2_WDT);
}
}
static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
{
FslIMX6ULState *s = FSL_IMX6UL(dev);
int i;
qemu_irq irq;
char name[NAME_SIZE];
if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
return;
}
for (i = 0; i < smp_cpus; i++) {
Object *o = OBJECT(&s->cpu[i]);
object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
/* On uniprocessor, the CBAR is set to 0 */
if (smp_cpus > 1) {
object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
"reset-cbar", &error_abort);
}
if (i) {
/* Secondary CPUs start in PSCI powered-down state */
object_property_set_bool(o, true,
"start-powered-off", &error_abort);
}
object_property_set_bool(o, true, "realized", &error_abort);
}
/*
* A7MPCORE
*/
object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
&error_abort);
object_property_set_int(OBJECT(&s->a7mpcore),
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
for (i = 0; i < smp_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
DeviceState *d = DEVICE(qemu_get_cpu(i));
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
}
/*
* A7MPCORE DAP
*/
create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
0x100000);
/*
* GPT 1, 2
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
FSL_IMX6UL_GPT1_ADDR,
FSL_IMX6UL_GPT2_ADDR,
};
static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
FSL_IMX6UL_GPT1_IRQ,
FSL_IMX6UL_GPT2_IRQ,
};
s->gpt[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
FSL_IMX6UL_GPTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_GPTn_IRQ[i]));
}
/*
* EPIT 1, 2
*/
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
FSL_IMX6UL_EPIT1_ADDR,
FSL_IMX6UL_EPIT2_ADDR,
};
static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
FSL_IMX6UL_EPIT1_IRQ,
FSL_IMX6UL_EPIT2_IRQ,
};
s->epit[i].ccm = IMX_CCM(&s->ccm);
object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
FSL_IMX6UL_EPITn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_EPITn_IRQ[i]));
}
/*
* GPIO
*/
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
FSL_IMX6UL_GPIO1_ADDR,
FSL_IMX6UL_GPIO2_ADDR,
FSL_IMX6UL_GPIO3_ADDR,
FSL_IMX6UL_GPIO4_ADDR,
FSL_IMX6UL_GPIO5_ADDR,
};
static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
FSL_IMX6UL_GPIO1_LOW_IRQ,
FSL_IMX6UL_GPIO2_LOW_IRQ,
FSL_IMX6UL_GPIO3_LOW_IRQ,
FSL_IMX6UL_GPIO4_LOW_IRQ,
FSL_IMX6UL_GPIO5_LOW_IRQ,
};
static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
FSL_IMX6UL_GPIO1_HIGH_IRQ,
FSL_IMX6UL_GPIO2_HIGH_IRQ,
FSL_IMX6UL_GPIO3_HIGH_IRQ,
FSL_IMX6UL_GPIO4_HIGH_IRQ,
FSL_IMX6UL_GPIO5_HIGH_IRQ,
};
object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
FSL_IMX6UL_GPIOn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
}
/*
* IOMUXC and IOMUXC_GPR
*/
for (i = 0; i < 1; i++) {
static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
FSL_IMX6UL_IOMUXC_ADDR,
FSL_IMX6UL_IOMUXC_GPR_ADDR,
};
snprintf(name, NAME_SIZE, "iomuxc%d", i);
create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
}
/*
* CCM
*/
object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
/*
* SRC
*/
object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
/*
* GPCv2
*/
object_property_set_bool(OBJECT(&s->gpcv2), true,
"realized", &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
/* Initialize all ECSPI */
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
FSL_IMX6UL_ECSPI1_ADDR,
FSL_IMX6UL_ECSPI2_ADDR,
FSL_IMX6UL_ECSPI3_ADDR,
FSL_IMX6UL_ECSPI4_ADDR,
};
static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
FSL_IMX6UL_ECSPI1_IRQ,
FSL_IMX6UL_ECSPI2_IRQ,
FSL_IMX6UL_ECSPI3_IRQ,
FSL_IMX6UL_ECSPI4_IRQ,
};
/* Initialize the SPI */
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX6UL_SPIn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_SPIn_IRQ[i]));
}
/*
* I2C
*/
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
FSL_IMX6UL_I2C1_ADDR,
FSL_IMX6UL_I2C2_ADDR,
FSL_IMX6UL_I2C3_ADDR,
FSL_IMX6UL_I2C4_ADDR,
};
static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
FSL_IMX6UL_I2C1_IRQ,
FSL_IMX6UL_I2C2_IRQ,
FSL_IMX6UL_I2C3_IRQ,
FSL_IMX6UL_I2C4_IRQ,
};
object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_I2Cn_IRQ[i]));
}
/*
* UART
*/
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
FSL_IMX6UL_UART1_ADDR,
FSL_IMX6UL_UART2_ADDR,
FSL_IMX6UL_UART3_ADDR,
FSL_IMX6UL_UART4_ADDR,
FSL_IMX6UL_UART5_ADDR,
FSL_IMX6UL_UART6_ADDR,
FSL_IMX6UL_UART7_ADDR,
FSL_IMX6UL_UART8_ADDR,
};
static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
FSL_IMX6UL_UART1_IRQ,
FSL_IMX6UL_UART2_IRQ,
FSL_IMX6UL_UART3_IRQ,
FSL_IMX6UL_UART4_IRQ,
FSL_IMX6UL_UART5_IRQ,
FSL_IMX6UL_UART6_IRQ,
FSL_IMX6UL_UART7_IRQ,
FSL_IMX6UL_UART8_IRQ,
};
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
FSL_IMX6UL_UARTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_UARTn_IRQ[i]));
}
/*
* Ethernet
*/
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
FSL_IMX6UL_ENET1_ADDR,
FSL_IMX6UL_ENET2_ADDR,
};
static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
FSL_IMX6UL_ENET1_IRQ,
FSL_IMX6UL_ENET2_IRQ,
};
static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
FSL_IMX6UL_ENET1_TIMER_IRQ,
FSL_IMX6UL_ENET2_TIMER_IRQ,
};
object_property_set_uint(OBJECT(&s->eth[i]),
FSL_IMX6UL_ETH_NUM_TX_RINGS,
"tx-ring-num", &error_abort);
qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
FSL_IMX6UL_ENETn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_ENETn_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
}
/*
* USDHC
*/
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
FSL_IMX6UL_USDHC1_ADDR,
FSL_IMX6UL_USDHC2_ADDR,
};
static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
FSL_IMX6UL_USDHC1_IRQ,
FSL_IMX6UL_USDHC2_IRQ,
};
object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
FSL_IMX6UL_USDHCn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
FSL_IMX6UL_USDHCn_IRQ[i]));
}
/*
* SNVS
*/
object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
/*
* Watchdog
*/
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
FSL_IMX6UL_WDOG1_ADDR,
FSL_IMX6UL_WDOG2_ADDR,
FSL_IMX6UL_WDOG3_ADDR,
};
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
FSL_IMX6UL_WDOGn_ADDR[i]);
}
/*
* GPR
*/
object_property_set_bool(OBJECT(&s->gpr), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
/*
* SDMA
*/
create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
/*
* APHB_DMA
*/
create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
FSL_IMX6UL_APBH_DMA_SIZE);
/*
* ADCs
*/
for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
FSL_IMX6UL_ADC1_ADDR,
FSL_IMX6UL_ADC2_ADDR,
};
snprintf(name, NAME_SIZE, "adc%d", i);
create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
}
/*
* LCD
*/
create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
/*
* ROM memory
*/
memory_region_init_rom(&s->rom, NULL, "imx6ul.rom",
FSL_IMX6UL_ROM_SIZE, &error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
&s->rom);
/*
* CAAM memory
*/
memory_region_init_rom(&s->caam, NULL, "imx6ul.caam",
FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
&s->caam);
/*
* OCRAM memory
*/
memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
FSL_IMX6UL_OCRAM_MEM_SIZE,
&error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
&s->ocram);
/*
* internal OCRAM (128 KB) is aliased over 512 KB
*/
memory_region_init_alias(&s->ocram_alias, NULL, "imx6ul.ocram_alias",
&s->ocram, 0, FSL_IMX6UL_OCRAM_ALIAS_SIZE);
memory_region_add_subregion(get_system_memory(),
FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
}
static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = fsl_imx6ul_realize;
dc->desc = "i.MX6UL SOC";
/* Reason: Uses serial_hds and nd_table in realize() directly */
dc->user_creatable = false;
}
static const TypeInfo fsl_imx6ul_type_info = {
.name = TYPE_FSL_IMX6UL,
.parent = TYPE_DEVICE,
.instance_size = sizeof(FslIMX6ULState),
.instance_init = fsl_imx6ul_init,
.class_init = fsl_imx6ul_class_init,
};
static void fsl_imx6ul_register_types(void)
{
type_register_static(&fsl_imx6ul_type_info);
}
type_init(fsl_imx6ul_register_types)

85
hw/arm/mcimx6ul-evk.c Normal file
View File

@ -0,0 +1,85 @@
/*
* Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
*
* MCIMX6UL_EVK Board System emulation.
*
* This code is licensed under the GPL, version 2 or later.
* See the file `COPYING' in the top level directory.
*
* It (partially) emulates a mcimx6ul_evk board, with a Freescale
* i.MX6ul SoC
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
typedef struct {
FslIMX6ULState soc;
MemoryRegion ram;
} MCIMX6ULEVK;
static void mcimx6ul_evk_init(MachineState *machine)
{
static struct arm_boot_info boot_info;
MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1);
int i;
if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) {
error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
machine->ram_size, FSL_IMX6UL_MMDC_SIZE);
exit(1);
}
boot_info = (struct arm_boot_info) {
.loader_start = FSL_IMX6UL_MMDC_ADDR,
.board_id = -1,
.ram_size = machine->ram_size,
.kernel_filename = machine->kernel_filename,
.kernel_cmdline = machine->kernel_cmdline,
.initrd_filename = machine->initrd_filename,
.nb_cpus = smp_cpus,
};
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_FSL_IMX6UL, &error_fatal, NULL);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram",
machine->ram_size);
memory_region_add_subregion(get_system_memory(),
FSL_IMX6UL_MMDC_ADDR, &s->ram);
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
BusState *bus;
DeviceState *carddev;
DriveInfo *di;
BlockBackend *blk;
di = drive_get_next(IF_SD);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus");
carddev = qdev_create(bus, TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true,
"realized", &error_fatal);
}
if (!qtest_enabled()) {
arm_load_kernel(&s->soc.cpu[0], &boot_info);
}
}
static void mcimx6ul_evk_machine_init(MachineClass *mc)
{
mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)";
mc->init = mcimx6ul_evk_init;
mc->max_cpus = FSL_IMX6UL_NUM_CPUS;
}
DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)

32
hw/arm/mps2-tz.c
View File

@ -107,16 +107,6 @@ static void make_ram_alias(MemoryRegion *mr, const char *name,
memory_region_add_subregion(get_system_memory(), base, mr);
}
static void init_sysbus_child(Object *parent, const char *childname,
void *child, size_t childsize,
const char *childtype)
{
object_initialize(child, childsize, childtype);
object_property_add_child(parent, childname, OBJECT(child), &error_abort);
qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
}
/* Most of the devices in the AN505 FPGA image sit behind
* Peripheral Protection Controllers. These data structures
* define the layout of which devices sit behind which PPCs.
@ -149,9 +139,9 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
*/
UnimplementedDeviceState *uds = opaque;
init_sysbus_child(OBJECT(mms), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
sysbus_init_child_obj(OBJECT(mms), name, uds,
sizeof(UnimplementedDeviceState),
TYPE_UNIMPLEMENTED_DEVICE);
qdev_prop_set_string(DEVICE(uds), "name", name);
qdev_prop_set_uint64(DEVICE(uds), "size", size);
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
@ -170,8 +160,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
DeviceState *iotkitdev = DEVICE(&mms->iotkit);
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
init_sysbus_child(OBJECT(mms), name, uart,
sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART);
sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
TYPE_CMSDK_APB_UART);
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
@ -248,8 +238,8 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
init_sysbus_child(OBJECT(mms), mpcname, mpc,
sizeof(mms->ssram_mpc[0]), TYPE_TZ_MPC);
sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
TYPE_TZ_MPC);
object_property_set_link(OBJECT(mpc), OBJECT(ssram),
"downstream", &error_fatal);
object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
@ -288,8 +278,8 @@ static void mps2tz_common_init(MachineState *machine)
exit(1);
}
init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit,
sizeof(mms->iotkit), TYPE_IOTKIT);
sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
sizeof(mms->iotkit), TYPE_IOTKIT);
iotkitdev = DEVICE(&mms->iotkit);
object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
"memory", &error_abort);
@ -421,8 +411,8 @@ static void mps2tz_common_init(MachineState *machine)
int port;
char *gpioname;
init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc,
sizeof(TZPPC), TYPE_TZ_PPC);
sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
sizeof(TZPPC), TYPE_TZ_PPC);
ppcdev = DEVICE(ppc);
for (port = 0; port < TZ_NUM_PORTS; port++) {

1
hw/arm/mps2.c
View File

@ -186,6 +186,7 @@ static void mps2_common_init(MachineState *machine)
g_assert_not_reached();
}
qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
"memory", &error_abort);
object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",

1
hw/arm/msf2-soc.c
View File

@ -117,6 +117,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 81);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);

1
hw/arm/stellaris.c
View File

@ -1304,6 +1304,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
nvic = qdev_create(NULL, TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
"memory", &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */

1
hw/arm/stm32f205_soc.c
View File

@ -109,6 +109,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
"memory", &error_abort);
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);

4
hw/core/generic-loader.c
View File

@ -147,6 +147,10 @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
size = load_uimage_as(s->file, &entry, NULL, NULL, NULL, NULL,
as);
}
if (size < 0) {
size = load_targphys_hex_as(s->file, &entry, as);
}
}
if (size < 0 || s->force_raw) {

302
hw/core/loader.c
View File

@ -840,6 +840,8 @@ struct Rom {
char *fw_dir;
char *fw_file;
bool committed;
hwaddr addr;
QTAILQ_ENTRY(Rom) next;
};
@ -847,6 +849,17 @@ struct Rom {
static FWCfgState *fw_cfg;
static QTAILQ_HEAD(, Rom) roms = QTAILQ_HEAD_INITIALIZER(roms);
/* rom->data must be heap-allocated (do not use with rom_add_elf_program()) */
static void rom_free(Rom *rom)
{
g_free(rom->data);
g_free(rom->path);
g_free(rom->name);
g_free(rom->fw_dir);
g_free(rom->fw_file);
g_free(rom);
}
static inline bool rom_order_compare(Rom *rom, Rom *item)
{
return ((uintptr_t)(void *)rom->as > (uintptr_t)(void *)item->as) ||
@ -866,6 +879,8 @@ static void rom_insert(Rom *rom)
rom->as = &address_space_memory;
}
rom->committed = false;
/* List is ordered by load address in the same address space */
QTAILQ_FOREACH(item, &roms, next) {
if (rom_order_compare(rom, item)) {
@ -995,15 +1010,7 @@ err:
if (fd != -1)
close(fd);
g_free(rom->data);
g_free(rom->path);
g_free(rom->name);
if (fw_dir) {
g_free(rom->fw_dir);
g_free(rom->fw_file);
}
g_free(rom);
rom_free(rom);
return -1;
}
@ -1165,6 +1172,34 @@ void rom_reset_order_override(void)
fw_cfg_reset_order_override(fw_cfg);
}
void rom_transaction_begin(void)
{
Rom *rom;
/* Ignore ROMs added without the transaction API */
QTAILQ_FOREACH(rom, &roms, next) {
rom->committed = true;
}
}
void rom_transaction_end(bool commit)
{
Rom *rom;
Rom *tmp;
QTAILQ_FOREACH_SAFE(rom, &roms, next, tmp) {
if (rom->committed) {
continue;
}
if (commit) {
rom->committed = true;
} else {
QTAILQ_REMOVE(&roms, rom, next);
rom_free(rom);
}
}
}
static Rom *find_rom(hwaddr addr, size_t size)
{
Rom *rom;
@ -1286,3 +1321,252 @@ void hmp_info_roms(Monitor *mon, const QDict *qdict)
}
}
}
typedef enum HexRecord HexRecord;
enum HexRecord {
DATA_RECORD = 0,
EOF_RECORD,
EXT_SEG_ADDR_RECORD,
START_SEG_ADDR_RECORD,
EXT_LINEAR_ADDR_RECORD,
START_LINEAR_ADDR_RECORD,
};
/* Each record contains a 16-bit address which is combined with the upper 16
* bits of the implicit "next address" to form a 32-bit address.
*/
#define NEXT_ADDR_MASK 0xffff0000
#define DATA_FIELD_MAX_LEN 0xff
#define LEN_EXCEPT_DATA 0x5
/* 0x5 = sizeof(byte_count) + sizeof(address) + sizeof(record_type) +
* sizeof(checksum) */
typedef struct {
uint8_t byte_count;
uint16_t address;
uint8_t record_type;
uint8_t data[DATA_FIELD_MAX_LEN];
uint8_t checksum;
} HexLine;
/* return 0 or -1 if error */
static bool parse_record(HexLine *line, uint8_t *our_checksum, const uint8_t c,
uint32_t *index, const bool in_process)
{
/* +-------+---------------+-------+---------------------+--------+
* | byte | |record | | |
* | count | address | type | data |checksum|
* +-------+---------------+-------+---------------------+--------+
* ^ ^ ^ ^ ^ ^
* |1 byte | 2 bytes |1 byte | 0-255 bytes | 1 byte |
*/
uint8_t value = 0;
uint32_t idx = *index;
/* ignore space */
if (g_ascii_isspace(c)) {
return true;
}
if (!g_ascii_isxdigit(c) || !in_process) {
return false;
}
value = g_ascii_xdigit_value(c);
value = (idx & 0x1) ? (value & 0xf) : (value << 4);
if (idx < 2) {
line->byte_count |= value;
} else if (2 <= idx && idx < 6) {
line->address <<= 4;
line->address += g_ascii_xdigit_value(c);
} else if (6 <= idx && idx < 8) {
line->record_type |= value;
} else if (8 <= idx && idx < 8 + 2 * line->byte_count) {
line->data[(idx - 8) >> 1] |= value;
} else if (8 + 2 * line->byte_count <= idx &&
idx < 10 + 2 * line->byte_count) {
line->checksum |= value;
} else {
return false;
}
*our_checksum += value;
++(*index);
return true;
}
typedef struct {
const char *filename;
HexLine line;
uint8_t *bin_buf;
hwaddr *start_addr;
int total_size;
uint32_t next_address_to_write;
uint32_t current_address;
uint32_t current_rom_index;
uint32_t rom_start_address;
AddressSpace *as;
} HexParser;
/* return size or -1 if error */
static int handle_record_type(HexParser *parser)
{
HexLine *line = &(parser->line);
switch (line->record_type) {
case DATA_RECORD:
parser->current_address =
(parser->next_address_to_write & NEXT_ADDR_MASK) | line->address;
/* verify this is a contiguous block of memory */
if (parser->current_address != parser->next_address_to_write) {
if (parser->current_rom_index != 0) {
rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
parser->current_rom_index,
parser->rom_start_address, parser->as);
}
parser->rom_start_address = parser->current_address;
parser->current_rom_index = 0;
}
/* copy from line buffer to output bin_buf */
memcpy(parser->bin_buf + parser->current_rom_index, line->data,
line->byte_count);
parser->current_rom_index += line->byte_count;
parser->total_size += line->byte_count;
/* save next address to write */
parser->next_address_to_write =
parser->current_address + line->byte_count;
break;
case EOF_RECORD:
if (parser->current_rom_index != 0) {
rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
parser->current_rom_index,
parser->rom_start_address, parser->as);
}
return parser->total_size;
case EXT_SEG_ADDR_RECORD:
case EXT_LINEAR_ADDR_RECORD:
if (line->byte_count != 2 && line->address != 0) {
return -1;
}
if (parser->current_rom_index != 0) {
rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
parser->current_rom_index,
parser->rom_start_address, parser->as);
}
/* save next address to write,
* in case of non-contiguous block of memory */
parser->next_address_to_write = (line->data[0] << 12) |
(line->data[1] << 4);
if (line->record_type == EXT_LINEAR_ADDR_RECORD) {
parser->next_address_to_write <<= 12;
}
parser->rom_start_address = parser->next_address_to_write;
parser->current_rom_index = 0;
break;
case START_SEG_ADDR_RECORD:
if (line->byte_count != 4 && line->address != 0) {
return -1;
}
/* x86 16-bit CS:IP segmented addressing */
*(parser->start_addr) = (((line->data[0] << 8) | line->data[1]) << 4) +
((line->data[2] << 8) | line->data[3]);
break;
case START_LINEAR_ADDR_RECORD:
if (line->byte_count != 4 && line->address != 0) {
return -1;
}
*(parser->start_addr) = ldl_be_p(line->data);
break;
default:
return -1;
}
return parser->total_size;
}
/* return size or -1 if error */
static int parse_hex_blob(const char *filename, hwaddr *addr, uint8_t *hex_blob,
size_t hex_blob_size, AddressSpace *as)
{
bool in_process = false; /* avoid re-enter and
* check whether record begin with ':' */
uint8_t *end = hex_blob + hex_blob_size;
uint8_t our_checksum = 0;
uint32_t record_index = 0;
HexParser parser = {
.filename = filename,
.bin_buf = g_malloc(hex_blob_size),
.start_addr = addr,
.as = as,
};
rom_transaction_begin();
for (; hex_blob < end; ++hex_blob) {
switch (*hex_blob) {
case '\r':
case '\n':
if (!in_process) {
break;
}
in_process = false;
if ((LEN_EXCEPT_DATA + parser.line.byte_count) * 2 !=
record_index ||
our_checksum != 0) {
parser.total_size = -1;
goto out;
}
if (handle_record_type(&parser) == -1) {
parser.total_size = -1;
goto out;
}
break;
/* start of a new record. */
case ':':
memset(&parser.line, 0, sizeof(HexLine));
in_process = true;
record_index = 0;
break;
/* decoding lines */
default:
if (!parse_record(&parser.line, &our_checksum, *hex_blob,
&record_index, in_process)) {
parser.total_size = -1;
goto out;
}
break;
}
}
out:
g_free(parser.bin_buf);
rom_transaction_end(parser.total_size != -1);
return parser.total_size;
}
/* return size or -1 if error */
int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as)
{
gsize hex_blob_size;
gchar *hex_blob;
int total_size = 0;
if (!g_file_get_contents(filename, &hex_blob, &hex_blob_size, NULL)) {
return -1;
}
total_size = parse_hex_blob(filename, entry, (uint8_t *)hex_blob,
hex_blob_size, as);
g_free(hex_blob);
return total_size;
}

1
hw/misc/Makefile.objs
View File

@ -36,6 +36,7 @@ obj-$(CONFIG_IMX) += imx_ccm.o
obj-$(CONFIG_IMX) += imx31_ccm.o
obj-$(CONFIG_IMX) += imx25_ccm.o
obj-$(CONFIG_IMX) += imx6_ccm.o
obj-$(CONFIG_IMX) += imx6ul_ccm.o
obj-$(CONFIG_IMX) += imx6_src.o
obj-$(CONFIG_IMX) += imx7_ccm.o
obj-$(CONFIG_IMX) += imx2_wdt.o

55
hw/misc/aspeed_sdmc.c
View File

@ -23,6 +23,14 @@
/* Configuration Register */
#define R_CONF (0x04 / 4)
/* Control/Status Register #1 (ast2500) */
#define R_STATUS1 (0x60 / 4)
#define PHY_BUSY_STATE BIT(0)
#define R_ECC_TEST_CTRL (0x70 / 4)
#define ECC_TEST_FINISHED BIT(12)
#define ECC_TEST_FAIL BIT(13)
/*
* Configuration register Ox4 (for Aspeed AST2400 SOC)
*
@ -126,15 +134,33 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
data &= ~ASPEED_SDMC_READONLY_MASK;
data |= s->fixed_conf;
break;
case AST2500_A0_SILICON_REV:
case AST2500_A1_SILICON_REV:
data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
data |= s->fixed_conf;
break;
default:
g_assert_not_reached();
}
}
if (s->silicon_rev == AST2500_A0_SILICON_REV ||
s->silicon_rev == AST2500_A1_SILICON_REV) {
switch (addr) {
case R_STATUS1:
/* Will never return 'busy' */
data &= ~PHY_BUSY_STATE;
break;
case R_ECC_TEST_CTRL:
/* Always done, always happy */
data |= ECC_TEST_FINISHED;
data &= ~ECC_TEST_FAIL;
break;
default:
break;
}
}
s->regs[addr] = data;
}
@ -198,25 +224,7 @@ static void aspeed_sdmc_reset(DeviceState *dev)
memset(s->regs, 0, sizeof(s->regs));
/* Set ram size bit and defaults values */
switch (s->silicon_rev) {
case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
s->regs[R_CONF] |=
ASPEED_SDMC_VGA_COMPAT |
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
break;
case AST2500_A0_SILICON_REV:
case AST2500_A1_SILICON_REV:
s->regs[R_CONF] |=
ASPEED_SDMC_HW_VERSION(1) |
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
break;
default:
g_assert_not_reached();
}
s->regs[R_CONF] = s->fixed_conf;
}
static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
@ -234,10 +242,18 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
case AST2400_A0_SILICON_REV:
case AST2400_A1_SILICON_REV:
s->ram_bits = ast2400_rambits(s);
s->max_ram_size = 512 << 20;
s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
break;
case AST2500_A0_SILICON_REV:
case AST2500_A1_SILICON_REV:
s->ram_bits = ast2500_rambits(s);
s->max_ram_size = 1024 << 20;
s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
ASPEED_SDMC_CACHE_INITIAL_DONE |
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
break;
default:
g_assert_not_reached();
@ -261,6 +277,7 @@ static const VMStateDescription vmstate_aspeed_sdmc = {
static Property aspeed_sdmc_properties[] = {
DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};

886
hw/misc/imx6ul_ccm.c Normal file
View File

@ -0,0 +1,886 @@
/*
* IMX6UL Clock Control Module
*
* Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
* To get the timer frequencies right, we need to emulate at least part of
* the CCM.
*/
#include "qemu/osdep.h"
#include "hw/registerfields.h"
#include "hw/misc/imx6ul_ccm.h"
#include "qemu/log.h"
#include "trace.h"
static const char *imx6ul_ccm_reg_name(uint32_t reg)
{
static char unknown[20];
switch (reg) {
case CCM_CCR:
return "CCR";
case CCM_CCDR:
return "CCDR";
case CCM_CSR:
return "CSR";
case CCM_CCSR:
return "CCSR";
case CCM_CACRR:
return "CACRR";
case CCM_CBCDR:
return "CBCDR";
case CCM_CBCMR:
return "CBCMR";
case CCM_CSCMR1:
return "CSCMR1";
case CCM_CSCMR2:
return "CSCMR2";
case CCM_CSCDR1:
return "CSCDR1";
case CCM_CS1CDR:
return "CS1CDR";
case CCM_CS2CDR:
return "CS2CDR";
case CCM_CDCDR:
return "CDCDR";
case CCM_CHSCCDR:
return "CHSCCDR";
case CCM_CSCDR2:
return "CSCDR2";
case CCM_CSCDR3:
return "CSCDR3";
case CCM_CDHIPR:
return "CDHIPR";
case CCM_CTOR:
return "CTOR";
case CCM_CLPCR:
return "CLPCR";
case CCM_CISR:
return "CISR";
case CCM_CIMR:
return "CIMR";
case CCM_CCOSR:
return "CCOSR";
case CCM_CGPR:
return "CGPR";
case CCM_CCGR0:
return "CCGR0";
case CCM_CCGR1:
return "CCGR1";
case CCM_CCGR2:
return "CCGR2";
case CCM_CCGR3:
return "CCGR3";
case CCM_CCGR4:
return "CCGR4";
case CCM_CCGR5:
return "CCGR5";
case CCM_CCGR6:
return "CCGR6";
case CCM_CMEOR:
return "CMEOR";
default:
sprintf(unknown, "%d ?", reg);
return unknown;
}
}
static const char *imx6ul_analog_reg_name(uint32_t reg)
{
static char unknown[20];
switch (reg) {
case CCM_ANALOG_PLL_ARM:
return "PLL_ARM";
case CCM_ANALOG_PLL_ARM_SET:
return "PLL_ARM_SET";
case CCM_ANALOG_PLL_ARM_CLR:
return "PLL_ARM_CLR";
case CCM_ANALOG_PLL_ARM_TOG:
return "PLL_ARM_TOG";
case CCM_ANALOG_PLL_USB1:
return "PLL_USB1";
case CCM_ANALOG_PLL_USB1_SET:
return "PLL_USB1_SET";
case CCM_ANALOG_PLL_USB1_CLR:
return "PLL_USB1_CLR";
case CCM_ANALOG_PLL_USB1_TOG:
return "PLL_USB1_TOG";
case CCM_ANALOG_PLL_USB2:
return "PLL_USB2";
case CCM_ANALOG_PLL_USB2_SET:
return "PLL_USB2_SET";
case CCM_ANALOG_PLL_USB2_CLR:
return "PLL_USB2_CLR";
case CCM_ANALOG_PLL_USB2_TOG:
return "PLL_USB2_TOG";
case CCM_ANALOG_PLL_SYS:
return "PLL_SYS";
case CCM_ANALOG_PLL_SYS_SET:
return "PLL_SYS_SET";
case CCM_ANALOG_PLL_SYS_CLR:
return "PLL_SYS_CLR";
case CCM_ANALOG_PLL_SYS_TOG:
return "PLL_SYS_TOG";
case CCM_ANALOG_PLL_SYS_SS:
return "PLL_SYS_SS";
case CCM_ANALOG_PLL_SYS_NUM:
return "PLL_SYS_NUM";
case CCM_ANALOG_PLL_SYS_DENOM:
return "PLL_SYS_DENOM";
case CCM_ANALOG_PLL_AUDIO:
return "PLL_AUDIO";
case CCM_ANALOG_PLL_AUDIO_SET:
return "PLL_AUDIO_SET";
case CCM_ANALOG_PLL_AUDIO_CLR:
return "PLL_AUDIO_CLR";
case CCM_ANALOG_PLL_AUDIO_TOG:
return "PLL_AUDIO_TOG";
case CCM_ANALOG_PLL_AUDIO_NUM:
return "PLL_AUDIO_NUM";
case CCM_ANALOG_PLL_AUDIO_DENOM:
return "PLL_AUDIO_DENOM";
case CCM_ANALOG_PLL_VIDEO:
return "PLL_VIDEO";
case CCM_ANALOG_PLL_VIDEO_SET:
return "PLL_VIDEO_SET";
case CCM_ANALOG_PLL_VIDEO_CLR:
return "PLL_VIDEO_CLR";
case CCM_ANALOG_PLL_VIDEO_TOG:
return "PLL_VIDEO_TOG";
case CCM_ANALOG_PLL_VIDEO_NUM:
return "PLL_VIDEO_NUM";
case CCM_ANALOG_PLL_VIDEO_DENOM:
return "PLL_VIDEO_DENOM";
case CCM_ANALOG_PLL_ENET:
return "PLL_ENET";
case CCM_ANALOG_PLL_ENET_SET:
return "PLL_ENET_SET";
case CCM_ANALOG_PLL_ENET_CLR:
return "PLL_ENET_CLR";
case CCM_ANALOG_PLL_ENET_TOG:
return "PLL_ENET_TOG";
case CCM_ANALOG_PFD_480:
return "PFD_480";
case CCM_ANALOG_PFD_480_SET:
return "PFD_480_SET";
case CCM_ANALOG_PFD_480_CLR:
return "PFD_480_CLR";
case CCM_ANALOG_PFD_480_TOG:
return "PFD_480_TOG";
case CCM_ANALOG_PFD_528:
return "PFD_528";
case CCM_ANALOG_PFD_528_SET:
return "PFD_528_SET";
case CCM_ANALOG_PFD_528_CLR:
return "PFD_528_CLR";
case CCM_ANALOG_PFD_528_TOG:
return "PFD_528_TOG";
case CCM_ANALOG_MISC0:
return "MISC0";
case CCM_ANALOG_MISC0_SET:
return "MISC0_SET";
case CCM_ANALOG_MISC0_CLR:
return "MISC0_CLR";
case CCM_ANALOG_MISC0_TOG:
return "MISC0_TOG";
case CCM_ANALOG_MISC2:
return "MISC2";
case CCM_ANALOG_MISC2_SET:
return "MISC2_SET";
case CCM_ANALOG_MISC2_CLR:
return "MISC2_CLR";
case CCM_ANALOG_MISC2_TOG:
return "MISC2_TOG";
case PMU_REG_1P1:
return "PMU_REG_1P1";
case PMU_REG_3P0:
return "PMU_REG_3P0";
case PMU_REG_2P5:
return "PMU_REG_2P5";
case PMU_REG_CORE:
return "PMU_REG_CORE";
case PMU_MISC1:
return "PMU_MISC1";
case PMU_MISC1_SET:
return "PMU_MISC1_SET";
case PMU_MISC1_CLR:
return "PMU_MISC1_CLR";
case PMU_MISC1_TOG:
return "PMU_MISC1_TOG";
case USB_ANALOG_DIGPROG:
return "USB_ANALOG_DIGPROG";
default:
sprintf(unknown, "%d ?", reg);
return unknown;
}
}
#define CKIH_FREQ 24000000 /* 24MHz crystal input */
static const VMStateDescription vmstate_imx6ul_ccm = {
.name = TYPE_IMX6UL_CCM,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(ccm, IMX6ULCCMState, CCM_MAX),
VMSTATE_UINT32_ARRAY(analog, IMX6ULCCMState, CCM_ANALOG_MAX),
VMSTATE_END_OF_LIST()
},
};
static uint64_t imx6ul_analog_get_osc_clk(IMX6ULCCMState *dev)
{
uint64_t freq = CKIH_FREQ;
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_analog_get_pll2_clk(IMX6ULCCMState *dev)
{
uint64_t freq = imx6ul_analog_get_osc_clk(dev);
if (FIELD_EX32(dev->analog[CCM_ANALOG_PLL_SYS],
ANALOG_PLL_SYS, DIV_SELECT)) {
freq *= 22;
} else {
freq *= 20;
}
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_analog_get_pll3_clk(IMX6ULCCMState *dev)
{
uint64_t freq = imx6ul_analog_get_osc_clk(dev) * 20;
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_analog_get_pll2_pfd0_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
freq = imx6ul_analog_get_pll2_clk(dev) * 18
/ FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528],
ANALOG_PFD_528, PFD0_FRAC);
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_analog_get_pll2_pfd2_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
freq = imx6ul_analog_get_pll2_clk(dev) * 18
/ FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528],
ANALOG_PFD_528, PFD2_FRAC);
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_analog_pll2_bypass_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_periph_clk2_sel_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PERIPH_CLK2_SEL)) {
case 0:
freq = imx6ul_analog_get_pll3_clk(dev);
break;
case 1:
freq = imx6ul_analog_get_osc_clk(dev);
break;
case 2:
freq = imx6ul_analog_pll2_bypass_clk(dev);
break;
case 3:
/* We should never get there as 3 is a reserved value */
qemu_log_mask(LOG_GUEST_ERROR,
"[%s]%s: unsupported PERIPH_CLK2_SEL value 3\n",
TYPE_IMX6UL_CCM, __func__);
/* freq is set to 0 as we don't know what it should be */
break;
default:
g_assert_not_reached();
}
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_periph_clk_sel_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PRE_PERIPH_CLK_SEL)) {
case 0:
freq = imx6ul_analog_get_pll2_clk(dev);
break;
case 1:
freq = imx6ul_analog_get_pll2_pfd2_clk(dev);
break;
case 2:
freq = imx6ul_analog_get_pll2_pfd0_clk(dev);
break;
case 3:
freq = imx6ul_analog_get_pll2_pfd2_clk(dev) / 2;
break;
default:
g_assert_not_reached();
}
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_periph_clk2_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
freq = imx6ul_ccm_get_periph_clk2_sel_clk(dev)
/ (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK2_PODF));
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_periph_sel_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
switch (FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK_SEL)) {
case 0:
freq = imx6ul_ccm_get_periph_clk_sel_clk(dev);
break;
case 1:
freq = imx6ul_ccm_get_periph_clk2_clk(dev);
break;
default:
g_assert_not_reached();
}
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_ahb_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
freq = imx6ul_ccm_get_periph_sel_clk(dev)
/ (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, AHB_PODF));
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_ipg_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
freq = imx6ul_ccm_get_ahb_clk(dev)
/ (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, IPG_PODF));
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_per_sel_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
switch (FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_CLK_SEL)) {
case 0:
freq = imx6ul_ccm_get_ipg_clk(dev);
break;
case 1:
freq = imx6ul_analog_get_osc_clk(dev);
break;
default:
g_assert_not_reached();
}
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint64_t imx6ul_ccm_get_per_clk(IMX6ULCCMState *dev)
{
uint64_t freq = 0;
freq = imx6ul_ccm_get_per_sel_clk(dev)
/ (1 + FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_PODF));
trace_ccm_freq((uint32_t)freq);
return freq;
}
static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
{
uint32_t freq = 0;
IMX6ULCCMState *s = IMX6UL_CCM(dev);
switch (clock) {
case CLK_NONE:
break;
case CLK_IPG:
freq = imx6ul_ccm_get_ipg_clk(s);
break;
case CLK_IPG_HIGH:
freq = imx6ul_ccm_get_per_clk(s);
break;
case CLK_32k:
freq = CKIL_FREQ;
break;
case CLK_HIGH:
freq = CKIH_FREQ;
break;
case CLK_HIGH_DIV:
freq = CKIH_FREQ / 8;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
TYPE_IMX6UL_CCM, __func__, clock);
break;
}
trace_ccm_clock_freq(clock, freq);
return freq;
}
static void imx6ul_ccm_reset(DeviceState *dev)
{
IMX6ULCCMState *s = IMX6UL_CCM(dev);
trace_ccm_entry();
s->ccm[CCM_CCR] = 0x0401167F;
s->ccm[CCM_CCDR] = 0x00000000;
s->ccm[CCM_CSR] = 0x00000010;
s->ccm[CCM_CCSR] = 0x00000100;
s->ccm[CCM_CACRR] = 0x00000000;
s->ccm[CCM_CBCDR] = 0x00018D00;
s->ccm[CCM_CBCMR] = 0x24860324;
s->ccm[CCM_CSCMR1] = 0x04900080;
s->ccm[CCM_CSCMR2] = 0x03192F06;
s->ccm[CCM_CSCDR1] = 0x00490B00;
s->ccm[CCM_CS1CDR] = 0x0EC102C1;
s->ccm[CCM_CS2CDR] = 0x000336C1;
s->ccm[CCM_CDCDR] = 0x33F71F92;
s->ccm[CCM_CHSCCDR] = 0x000248A4;
s->ccm[CCM_CSCDR2] = 0x00029B48;
s->ccm[CCM_CSCDR3] = 0x00014841;
s->ccm[CCM_CDHIPR] = 0x00000000;
s->ccm[CCM_CTOR] = 0x00000000;
s->ccm[CCM_CLPCR] = 0x00000079;
s->ccm[CCM_CISR] = 0x00000000;
s->ccm[CCM_CIMR] = 0xFFFFFFFF;
s->ccm[CCM_CCOSR] = 0x000A0001;
s->ccm[CCM_CGPR] = 0x0000FE62;
s->ccm[CCM_CCGR0] = 0xFFFFFFFF;
s->ccm[CCM_CCGR1] = 0xFFFFFFFF;
s->ccm[CCM_CCGR2] = 0xFC3FFFFF;
s->ccm[CCM_CCGR3] = 0xFFFFFFFF;
s->ccm[CCM_CCGR4] = 0xFFFFFFFF;
s->ccm[CCM_CCGR5] = 0xFFFFFFFF;
s->ccm[CCM_CCGR6] = 0xFFFFFFFF;
s->ccm[CCM_CMEOR] = 0xFFFFFFFF;
s->analog[CCM_ANALOG_PLL_ARM] = 0x00013063;
s->analog[CCM_ANALOG_PLL_USB1] = 0x00012000;
s->analog[CCM_ANALOG_PLL_USB2] = 0x00012000;
s->analog[CCM_ANALOG_PLL_SYS] = 0x00013001;
s->analog[CCM_ANALOG_PLL_SYS_SS] = 0x00000000;
s->analog[CCM_ANALOG_PLL_SYS_NUM] = 0x00000000;
s->analog[CCM_ANALOG_PLL_SYS_DENOM] = 0x00000012;
s->analog[CCM_ANALOG_PLL_AUDIO] = 0x00011006;
s->analog[CCM_ANALOG_PLL_AUDIO_NUM] = 0x05F5E100;
s->analog[CCM_ANALOG_PLL_AUDIO_DENOM] = 0x2964619C;
s->analog[CCM_ANALOG_PLL_VIDEO] = 0x0001100C;
s->analog[CCM_ANALOG_PLL_VIDEO_NUM] = 0x05F5E100;
s->analog[CCM_ANALOG_PLL_VIDEO_DENOM] = 0x10A24447;
s->analog[CCM_ANALOG_PLL_ENET] = 0x00011001;
s->analog[CCM_ANALOG_PFD_480] = 0x1311100C;
s->analog[CCM_ANALOG_PFD_528] = 0x1018101B;
s->analog[PMU_REG_1P1] = 0x00001073;
s->analog[PMU_REG_3P0] = 0x00000F74;
s->analog[PMU_REG_2P5] = 0x00001073;
s->analog[PMU_REG_CORE] = 0x00482012;
s->analog[PMU_MISC0] = 0x04000000;
s->analog[PMU_MISC1] = 0x00000000;
s->analog[PMU_MISC2] = 0x00272727;
s->analog[PMU_LOWPWR_CTRL] = 0x00004009;
s->analog[USB_ANALOG_USB1_VBUS_DETECT] = 0x01000004;
s->analog[USB_ANALOG_USB1_CHRG_DETECT] = 0x00000000;
s->analog[USB_ANALOG_USB1_VBUS_DETECT_STAT] = 0x00000000;
s->analog[USB_ANALOG_USB1_CHRG_DETECT_STAT] = 0x00000000;
s->analog[USB_ANALOG_USB1_MISC] = 0x00000002;
s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x01000004;
s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000;
s->analog[USB_ANALOG_USB2_MISC] = 0x00000002;
s->analog[USB_ANALOG_DIGPROG] = 0x00640000;
/* all PLLs need to be locked */
s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK;
s->analog[CCM_ANALOG_PLL_USB1] |= CCM_ANALOG_PLL_LOCK;
s->analog[CCM_ANALOG_PLL_USB2] |= CCM_ANALOG_PLL_LOCK;
s->analog[CCM_ANALOG_PLL_SYS] |= CCM_ANALOG_PLL_LOCK;
s->analog[CCM_ANALOG_PLL_AUDIO] |= CCM_ANALOG_PLL_LOCK;
s->analog[CCM_ANALOG_PLL_VIDEO] |= CCM_ANALOG_PLL_LOCK;
s->analog[CCM_ANALOG_PLL_ENET] |= CCM_ANALOG_PLL_LOCK;
s->analog[TEMPMON_TEMPSENSE0] = 0x00000001;
s->analog[TEMPMON_TEMPSENSE1] = 0x00000001;
s->analog[TEMPMON_TEMPSENSE2] = 0x00000000;
}
static uint64_t imx6ul_ccm_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t value = 0;
uint32_t index = offset >> 2;
IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
assert(index < CCM_MAX);
value = s->ccm[index];
trace_ccm_read_reg(imx6ul_ccm_reg_name(index), (uint32_t)value);
return (uint64_t)value;
}
static void imx6ul_ccm_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
uint32_t index = offset >> 2;
IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
assert(index < CCM_MAX);
trace_ccm_write_reg(imx6ul_ccm_reg_name(index), (uint32_t)value);
/*
* We will do a better implementation later. In particular some bits
* cannot be written to.
*/
s->ccm[index] = (uint32_t)value;
}
static uint64_t imx6ul_analog_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t value;
uint32_t index = offset >> 2;
IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
assert(index < CCM_ANALOG_MAX);
switch (index) {
case CCM_ANALOG_PLL_ARM_SET:
case CCM_ANALOG_PLL_USB1_SET:
case CCM_ANALOG_PLL_USB2_SET:
case CCM_ANALOG_PLL_SYS_SET:
case CCM_ANALOG_PLL_AUDIO_SET:
case CCM_ANALOG_PLL_VIDEO_SET:
case CCM_ANALOG_PLL_ENET_SET:
case CCM_ANALOG_PFD_480_SET:
case CCM_ANALOG_PFD_528_SET:
case CCM_ANALOG_MISC0_SET:
case PMU_MISC1_SET:
case CCM_ANALOG_MISC2_SET:
case USB_ANALOG_USB1_VBUS_DETECT_SET:
case USB_ANALOG_USB1_CHRG_DETECT_SET:
case USB_ANALOG_USB1_MISC_SET:
case USB_ANALOG_USB2_VBUS_DETECT_SET:
case USB_ANALOG_USB2_CHRG_DETECT_SET:
case USB_ANALOG_USB2_MISC_SET:
case TEMPMON_TEMPSENSE0_SET:
case TEMPMON_TEMPSENSE1_SET:
case TEMPMON_TEMPSENSE2_SET:
/*
* All REG_NAME_SET register access are in fact targeting
* the REG_NAME register.
*/
value = s->analog[index - 1];
break;
case CCM_ANALOG_PLL_ARM_CLR:
case CCM_ANALOG_PLL_USB1_CLR:
case CCM_ANALOG_PLL_USB2_CLR:
case CCM_ANALOG_PLL_SYS_CLR:
case CCM_ANALOG_PLL_AUDIO_CLR:
case CCM_ANALOG_PLL_VIDEO_CLR:
case CCM_ANALOG_PLL_ENET_CLR:
case CCM_ANALOG_PFD_480_CLR:
case CCM_ANALOG_PFD_528_CLR:
case CCM_ANALOG_MISC0_CLR:
case PMU_MISC1_CLR:
case CCM_ANALOG_MISC2_CLR:
case USB_ANALOG_USB1_VBUS_DETECT_CLR:
case USB_ANALOG_USB1_CHRG_DETECT_CLR:
case USB_ANALOG_USB1_MISC_CLR:
case USB_ANALOG_USB2_VBUS_DETECT_CLR:
case USB_ANALOG_USB2_CHRG_DETECT_CLR:
case USB_ANALOG_USB2_MISC_CLR:
case TEMPMON_TEMPSENSE0_CLR:
case TEMPMON_TEMPSENSE1_CLR:
case TEMPMON_TEMPSENSE2_CLR:
/*
* All REG_NAME_CLR register access are in fact targeting
* the REG_NAME register.
*/
value = s->analog[index - 2];
break;
case CCM_ANALOG_PLL_ARM_TOG:
case CCM_ANALOG_PLL_USB1_TOG:
case CCM_ANALOG_PLL_USB2_TOG:
case CCM_ANALOG_PLL_SYS_TOG:
case CCM_ANALOG_PLL_AUDIO_TOG:
case CCM_ANALOG_PLL_VIDEO_TOG:
case CCM_ANALOG_PLL_ENET_TOG:
case CCM_ANALOG_PFD_480_TOG:
case CCM_ANALOG_PFD_528_TOG:
case CCM_ANALOG_MISC0_TOG:
case PMU_MISC1_TOG:
case CCM_ANALOG_MISC2_TOG:
case USB_ANALOG_USB1_VBUS_DETECT_TOG:
case USB_ANALOG_USB1_CHRG_DETECT_TOG:
case USB_ANALOG_USB1_MISC_TOG:
case USB_ANALOG_USB2_VBUS_DETECT_TOG:
case USB_ANALOG_USB2_CHRG_DETECT_TOG:
case USB_ANALOG_USB2_MISC_TOG:
case TEMPMON_TEMPSENSE0_TOG:
case TEMPMON_TEMPSENSE1_TOG:
case TEMPMON_TEMPSENSE2_TOG:
/*
* All REG_NAME_TOG register access are in fact targeting
* the REG_NAME register.
*/
value = s->analog[index - 3];
break;
default:
value = s->analog[index];
break;
}
trace_ccm_read_reg(imx6ul_analog_reg_name(index), (uint32_t)value);
return (uint64_t)value;
}
static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
uint32_t index = offset >> 2;
IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
assert(index < CCM_ANALOG_MAX);
trace_ccm_write_reg(imx6ul_analog_reg_name(index), (uint32_t)value);
switch (index) {
case CCM_ANALOG_PLL_ARM_SET:
case CCM_ANALOG_PLL_USB1_SET:
case CCM_ANALOG_PLL_USB2_SET:
case CCM_ANALOG_PLL_SYS_SET:
case CCM_ANALOG_PLL_AUDIO_SET:
case CCM_ANALOG_PLL_VIDEO_SET:
case CCM_ANALOG_PLL_ENET_SET:
case CCM_ANALOG_PFD_480_SET:
case CCM_ANALOG_PFD_528_SET:
case CCM_ANALOG_MISC0_SET:
case PMU_MISC1_SET:
case CCM_ANALOG_MISC2_SET:
case USB_ANALOG_USB1_VBUS_DETECT_SET:
case USB_ANALOG_USB1_CHRG_DETECT_SET:
case USB_ANALOG_USB1_MISC_SET:
case USB_ANALOG_USB2_VBUS_DETECT_SET:
case USB_ANALOG_USB2_CHRG_DETECT_SET:
case USB_ANALOG_USB2_MISC_SET:
/*
* All REG_NAME_SET register access are in fact targeting
* the REG_NAME register. So we change the value of the
* REG_NAME register, setting bits passed in the value.
*/
s->analog[index - 1] |= value;
break;
case CCM_ANALOG_PLL_ARM_CLR:
case CCM_ANALOG_PLL_USB1_CLR:
case CCM_ANALOG_PLL_USB2_CLR:
case CCM_ANALOG_PLL_SYS_CLR:
case CCM_ANALOG_PLL_AUDIO_CLR:
case CCM_ANALOG_PLL_VIDEO_CLR:
case CCM_ANALOG_PLL_ENET_CLR:
case CCM_ANALOG_PFD_480_CLR:
case CCM_ANALOG_PFD_528_CLR:
case CCM_ANALOG_MISC0_CLR:
case PMU_MISC1_CLR:
case CCM_ANALOG_MISC2_CLR:
case USB_ANALOG_USB1_VBUS_DETECT_CLR:
case USB_ANALOG_USB1_CHRG_DETECT_CLR:
case USB_ANALOG_USB1_MISC_CLR:
case USB_ANALOG_USB2_VBUS_DETECT_CLR:
case USB_ANALOG_USB2_CHRG_DETECT_CLR:
case USB_ANALOG_USB2_MISC_CLR:
/*
* All REG_NAME_CLR register access are in fact targeting
* the REG_NAME register. So we change the value of the
* REG_NAME register, unsetting bits passed in the value.
*/
s->analog[index - 2] &= ~value;
break;
case CCM_ANALOG_PLL_ARM_TOG:
case CCM_ANALOG_PLL_USB1_TOG:
case CCM_ANALOG_PLL_USB2_TOG:
case CCM_ANALOG_PLL_SYS_TOG:
case CCM_ANALOG_PLL_AUDIO_TOG:
case CCM_ANALOG_PLL_VIDEO_TOG:
case CCM_ANALOG_PLL_ENET_TOG:
case CCM_ANALOG_PFD_480_TOG:
case CCM_ANALOG_PFD_528_TOG:
case CCM_ANALOG_MISC0_TOG:
case PMU_MISC1_TOG:
case CCM_ANALOG_MISC2_TOG:
case USB_ANALOG_USB1_VBUS_DETECT_TOG:
case USB_ANALOG_USB1_CHRG_DETECT_TOG:
case USB_ANALOG_USB1_MISC_TOG:
case USB_ANALOG_USB2_VBUS_DETECT_TOG:
case USB_ANALOG_USB2_CHRG_DETECT_TOG:
case USB_ANALOG_USB2_MISC_TOG:
/*
* All REG_NAME_TOG register access are in fact targeting
* the REG_NAME register. So we change the value of the
* REG_NAME register, toggling bits passed in the value.
*/
s->analog[index - 3] ^= value;
break;
default:
/*
* We will do a better implementation later. In particular some bits
* cannot be written to.
*/
s->analog[index] = value;
break;
}
}
static const struct MemoryRegionOps imx6ul_ccm_ops = {
.read = imx6ul_ccm_read,
.write = imx6ul_ccm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
/*
* Our device would not work correctly if the guest was doing
* unaligned access. This might not be a limitation on the real
* device but in practice there is no reason for a guest to access
* this device unaligned.
*/
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static const struct MemoryRegionOps imx6ul_analog_ops = {
.read = imx6ul_analog_read,
.write = imx6ul_analog_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
/*
* Our device would not work correctly if the guest was doing
* unaligned access. This might not be a limitation on the real
* device but in practice there is no reason for a guest to access
* this device unaligned.
*/
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static void imx6ul_ccm_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
IMX6ULCCMState *s = IMX6UL_CCM(obj);
/* initialize a container for the all memory range */
memory_region_init(&s->container, OBJECT(dev), TYPE_IMX6UL_CCM, 0x8000);
/* We initialize an IO memory region for the CCM part */
memory_region_init_io(&s->ioccm, OBJECT(dev), &imx6ul_ccm_ops, s,
TYPE_IMX6UL_CCM ".ccm", CCM_MAX * sizeof(uint32_t));
/* Add the CCM as a subregion at offset 0 */
memory_region_add_subregion(&s->container, 0, &s->ioccm);
/* We initialize an IO memory region for the ANALOG part */
memory_region_init_io(&s->ioanalog, OBJECT(dev), &imx6ul_analog_ops, s,
TYPE_IMX6UL_CCM ".analog",
CCM_ANALOG_MAX * sizeof(uint32_t));
/* Add the ANALOG as a subregion at offset 0x4000 */
memory_region_add_subregion(&s->container, 0x4000, &s->ioanalog);
sysbus_init_mmio(sd, &s->container);
}
static void imx6ul_ccm_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
dc->reset = imx6ul_ccm_reset;
dc->vmsd = &vmstate_imx6ul_ccm;
dc->desc = "i.MX6UL Clock Control Module";
ccm->get_clock_frequency = imx6ul_ccm_get_clock_frequency;
}
static const TypeInfo imx6ul_ccm_info = {
.name = TYPE_IMX6UL_CCM,
.parent = TYPE_IMX_CCM,
.instance_size = sizeof(IMX6ULCCMState),
.instance_init = imx6ul_ccm_init,
.class_init = imx6ul_ccm_class_init,
};
static void imx6ul_ccm_register_types(void)
{
type_register_static(&imx6ul_ccm_info);
}
type_init(imx6ul_ccm_register_types)

7
hw/misc/trace-events
View File

@ -109,3 +109,10 @@ iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit Sec
iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u"
iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u"
iotkit_secctl_reset(void) "IoTKit SecCtl: reset"
# hw/misc/imx6ul_ccm.c
ccm_entry(void) "\n"
ccm_freq(uint32_t freq) "freq = %d\n"
ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d\n"
ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 "\n"
ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 "\n"

3
hw/ssi/imx_spi.c
View File

@ -208,8 +208,6 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
}
if (s->burst_length <= 0) {
s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
if (!imx_spi_is_multiple_master_burst(s)) {
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
break;
@ -219,6 +217,7 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
if (fifo32_is_empty(&s->tx_fifo)) {
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
}
/* TODO: We should also use TDR and RDR bits */

2
include/hw/arm/armv7m.h
View File

@ -43,6 +43,7 @@ typedef struct {
* devices will be automatically layered on top of this view.)
* + Property "idau": IDAU interface (forwarded to CPU object)
* + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
* + Property "enable-bitband": expose bitbanded IO
*/
typedef struct ARMv7MState {
/*< private >*/
@ -63,6 +64,7 @@ typedef struct ARMv7MState {
MemoryRegion *board_memory;
Object *idau;
uint32_t init_svtor;
bool enable_bitband;
} ARMv7MState;
#endif

339
include/hw/arm/fsl-imx6ul.h Normal file
View File

@ -0,0 +1,339 @@
/*
* Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
*
* i.MX6ul SoC definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef FSL_IMX6UL_H
#define FSL_IMX6UL_H
#include "hw/arm/arm.h"
#include "hw/cpu/a15mpcore.h"
#include "hw/misc/imx6ul_ccm.h"
#include "hw/misc/imx6_src.h"
#include "hw/misc/imx7_snvs.h"
#include "hw/misc/imx7_gpr.h"
#include "hw/intc/imx_gpcv2.h"
#include "hw/misc/imx2_wdt.h"
#include "hw/gpio/imx_gpio.h"
#include "hw/char/imx_serial.h"
#include "hw/timer/imx_gpt.h"
#include "hw/timer/imx_epit.h"
#include "hw/i2c/imx_i2c.h"
#include "hw/gpio/imx_gpio.h"
#include "hw/sd/sdhci.h"
#include "hw/ssi/imx_spi.h"
#include "hw/net/imx_fec.h"
#include "exec/memory.h"
#include "cpu.h"
#define TYPE_FSL_IMX6UL "fsl,imx6ul"
#define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL)
enum FslIMX6ULConfiguration {
FSL_IMX6UL_NUM_CPUS = 1,
FSL_IMX6UL_NUM_UARTS = 8,
FSL_IMX6UL_NUM_ETHS = 2,
FSL_IMX6UL_ETH_NUM_TX_RINGS = 2,
FSL_IMX6UL_NUM_USDHCS = 2,
FSL_IMX6UL_NUM_WDTS = 3,
FSL_IMX6UL_NUM_GPTS = 2,
FSL_IMX6UL_NUM_EPITS = 2,
FSL_IMX6UL_NUM_IOMUXCS = 2,
FSL_IMX6UL_NUM_GPIOS = 5,
FSL_IMX6UL_NUM_I2CS = 4,
FSL_IMX6UL_NUM_ECSPIS = 4,
FSL_IMX6UL_NUM_ADCS = 2,
};
typedef struct FslIMX6ULState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
ARMCPU cpu[FSL_IMX6UL_NUM_CPUS];
A15MPPrivState a7mpcore;
IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];
IMXGPIOState gpio[FSL_IMX6UL_NUM_GPIOS];
IMX6ULCCMState ccm;
IMX6SRCState src;
IMX7SNVSState snvs;
IMXGPCv2State gpcv2;
IMX7GPRState gpr;
IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
IMXFECState eth[FSL_IMX6UL_NUM_ETHS];
SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS];
IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS];
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
MemoryRegion ocram_alias;
} FslIMX6ULState;
enum FslIMX6ULMemoryMap {
FSL_IMX6UL_MMDC_ADDR = 0x80000000,
FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
/* AIPS-2 */
FSL_IMX6UL_UART6_ADDR = 0x021FC000,
FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
FSL_IMX6UL_UART5_ADDR = 0x021F4000,
FSL_IMX6UL_UART4_ADDR = 0x021F0000,
FSL_IMX6UL_UART3_ADDR = 0x021EC000,
FSL_IMX6UL_UART2_ADDR = 0x021E8000,
FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
FSL_IMX6UL_PXP_ADDR = 0x021CC000,
FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
FSL_IMX6UL_CSI_ADDR = 0x021C4000,
FSL_IMX6UL_CSU_ADDR = 0x021C0000,
FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
FSL_IMX6UL_EIM_ADDR = 0x021B8000,
FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
FSL_IMX6UL_ADC1_ADDR = 0x02198000,
FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
FSL_IMX6UL_ENET1_ADDR = 0x02188000,
FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000,
FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
FSL_IMX6UL_CAAM_ADDR = 0x02140000,
FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
/* AIPS-1 */
FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
FSL_IMX6UL_GPC_ADDR = 0x020DC000,
FSL_IMX6UL_SRC_ADDR = 0x020D8000,
FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
FSL_IMX6UL_CCM_ADDR = 0x020C4000,
FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
FSL_IMX6UL_KPP_ADDR = 0x020B8000,
FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
FSL_IMX6UL_GPT1_ADDR = 0x02098000,
FSL_IMX6UL_CAN2_ADDR = 0x02094000,
FSL_IMX6UL_CAN1_ADDR = 0x02090000,
FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
FSL_IMX6UL_PWM3_ADDR = 0x02088000,
FSL_IMX6UL_PWM2_ADDR = 0x02084000,
FSL_IMX6UL_PWM1_ADDR = 0x02080000,
FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
FSL_IMX6UL_BEE_ADDR = 0x02044000,
FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
FSL_IMX6UL_ASRC_ADDR = 0x02034000,
FSL_IMX6UL_SAI3_ADDR = 0x02030000,
FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
FSL_IMX6UL_SAI1_ADDR = 0x02028000,
FSL_IMX6UL_UART8_ADDR = 0x02024000,
FSL_IMX6UL_UART1_ADDR = 0x02020000,
FSL_IMX6UL_UART7_ADDR = 0x02018000,
FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024),
FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000,
FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000,
FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000,
FSL_IMX6UL_ROM_ADDR = 0x00000000,
FSL_IMX6UL_ROM_SIZE = 0x00018000,
};
enum FslIMX6ULIRQs {
FSL_IMX6UL_IOMUXC_IRQ = 0,
FSL_IMX6UL_DAP_IRQ = 1,
FSL_IMX6UL_SDMA_IRQ = 2,
FSL_IMX6UL_TSC_IRQ = 3,
FSL_IMX6UL_SNVS_IRQ = 4,
FSL_IMX6UL_LCDIF_IRQ = 5,
FSL_IMX6UL_BEE_IRQ = 6,
FSL_IMX6UL_CSI_IRQ = 7,
FSL_IMX6UL_PXP_IRQ = 8,
FSL_IMX6UL_SCTR1_IRQ = 9,
FSL_IMX6UL_SCTR2_IRQ = 10,
FSL_IMX6UL_WDOG3_IRQ = 11,
FSL_IMX6UL_APBH_DMA_IRQ = 13,
FSL_IMX6UL_WEIM_IRQ = 14,
FSL_IMX6UL_RAWNAND1_IRQ = 15,
FSL_IMX6UL_RAWNAND2_IRQ = 16,
FSL_IMX6UL_UART6_IRQ = 17,
FSL_IMX6UL_SRTC_IRQ = 19,
FSL_IMX6UL_SRTC_SEC_IRQ = 20,
FSL_IMX6UL_CSU_IRQ = 21,
FSL_IMX6UL_USDHC1_IRQ = 22,
FSL_IMX6UL_USDHC2_IRQ = 23,
FSL_IMX6UL_SAI3_IRQ = 24,
FSL_IMX6UL_SAI32_IRQ = 25,
FSL_IMX6UL_UART1_IRQ = 26,
FSL_IMX6UL_UART2_IRQ = 27,
FSL_IMX6UL_UART3_IRQ = 28,
FSL_IMX6UL_UART4_IRQ = 29,
FSL_IMX6UL_UART5_IRQ = 30,
FSL_IMX6UL_ECSPI1_IRQ = 31,
FSL_IMX6UL_ECSPI2_IRQ = 32,
FSL_IMX6UL_ECSPI3_IRQ = 33,
FSL_IMX6UL_ECSPI4_IRQ = 34,
FSL_IMX6UL_I2C4_IRQ = 35,
FSL_IMX6UL_I2C1_IRQ = 36,
FSL_IMX6UL_I2C2_IRQ = 37,
FSL_IMX6UL_I2C3_IRQ = 38,
FSL_IMX6UL_UART7_IRQ = 39,
FSL_IMX6UL_UART8_IRQ = 40,
FSL_IMX6UL_USB1_IRQ = 42,
FSL_IMX6UL_USB2_IRQ = 43,
FSL_IMX6UL_USB_PHY1_IRQ = 44,
FSL_IMX6UL_USB_PHY2_IRQ = 44,
FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
FSL_IMX6UL_CAAM_ERR_IRQ = 47,
FSL_IMX6UL_CAAM_RTIC_IRQ = 48,
FSL_IMX6UL_TEMP_IRQ = 49,
FSL_IMX6UL_ASRC_IRQ = 50,
FSL_IMX6UL_SPDIF_IRQ = 52,
FSL_IMX6UL_PMU_REG_IRQ = 54,
FSL_IMX6UL_GPT1_IRQ = 55,
FSL_IMX6UL_EPIT1_IRQ = 56,
FSL_IMX6UL_EPIT2_IRQ = 57,
FSL_IMX6UL_GPIO1_INT7_IRQ = 58,
FSL_IMX6UL_GPIO1_INT6_IRQ = 59,
FSL_IMX6UL_GPIO1_INT5_IRQ = 60,
FSL_IMX6UL_GPIO1_INT4_IRQ = 61,
FSL_IMX6UL_GPIO1_INT3_IRQ = 62,
FSL_IMX6UL_GPIO1_INT2_IRQ = 63,
FSL_IMX6UL_GPIO1_INT1_IRQ = 64,
FSL_IMX6UL_GPIO1_INT0_IRQ = 65,
FSL_IMX6UL_GPIO1_LOW_IRQ = 66,
FSL_IMX6UL_GPIO1_HIGH_IRQ = 67,
FSL_IMX6UL_GPIO2_LOW_IRQ = 68,
FSL_IMX6UL_GPIO2_HIGH_IRQ = 69,
FSL_IMX6UL_GPIO3_LOW_IRQ = 70,
FSL_IMX6UL_GPIO3_HIGH_IRQ = 71,
FSL_IMX6UL_GPIO4_LOW_IRQ = 72,
FSL_IMX6UL_GPIO4_HIGH_IRQ = 73,
FSL_IMX6UL_GPIO5_LOW_IRQ = 74,
FSL_IMX6UL_GPIO5_HIGH_IRQ = 75,
FSL_IMX6UL_WDOG1_IRQ = 80,
FSL_IMX6UL_WDOG2_IRQ = 81,
FSL_IMX6UL_KPP_IRQ = 82,
FSL_IMX6UL_PWM1_IRQ = 83,
FSL_IMX6UL_PWM2_IRQ = 84,
FSL_IMX6UL_PWM3_IRQ = 85,
FSL_IMX6UL_PWM4_IRQ = 86,
FSL_IMX6UL_CCM1_IRQ = 87,
FSL_IMX6UL_CCM2_IRQ = 88,
FSL_IMX6UL_GPC_IRQ = 89,
FSL_IMX6UL_SRC_IRQ = 91,
FSL_IMX6UL_CPU_PERF_IRQ = 94,
FSL_IMX6UL_CPU_CTI_IRQ = 95,
FSL_IMX6UL_SRC_WDOG_IRQ = 96,
FSL_IMX6UL_SAI1_IRQ = 97,
FSL_IMX6UL_SAI2_IRQ = 98,
FSL_IMX6UL_ADC1_IRQ = 100,
FSL_IMX6UL_ADC2_IRQ = 101,
FSL_IMX6UL_SJC_IRQ = 104,
FSL_IMX6UL_CAAM_RING0_IRQ = 105,
FSL_IMX6UL_CAAM_RING1_IRQ = 106,
FSL_IMX6UL_QSPI_IRQ = 107,
FSL_IMX6UL_TZASC_IRQ = 108,
FSL_IMX6UL_GPT2_IRQ = 109,
FSL_IMX6UL_CAN1_IRQ = 110,
FSL_IMX6UL_CAN2_IRQ = 111,
FSL_IMX6UL_SIM1_IRQ = 112,
FSL_IMX6UL_SIM2_IRQ = 113,
FSL_IMX6UL_PWM5_IRQ = 114,
FSL_IMX6UL_PWM6_IRQ = 115,
FSL_IMX6UL_PWM7_IRQ = 116,
FSL_IMX6UL_PWM8_IRQ = 117,
FSL_IMX6UL_ENET1_IRQ = 118,
FSL_IMX6UL_ENET1_TIMER_IRQ = 119,
FSL_IMX6UL_ENET2_IRQ = 120,
FSL_IMX6UL_ENET2_TIMER_IRQ = 121,
FSL_IMX6UL_PMU_CORE_IRQ = 127,
FSL_IMX6UL_MAX_IRQ = 128,
};
#endif /* FSL_IMX6UL_H */

31
include/hw/loader.h
View File

@ -28,6 +28,18 @@ ssize_t load_image_size(const char *filename, void *addr, size_t size);
int load_image_targphys_as(const char *filename,
hwaddr addr, uint64_t max_sz, AddressSpace *as);
/**load_targphys_hex_as:
* @filename: Path to the .hex file
* @entry: Store the entry point given by the .hex file
* @as: The AddressSpace to load the .hex file to. The value of
* address_space_memory is used if nothing is supplied here.
*
* Load a fixed .hex file into memory.
*
* Returns the size of the loaded .hex file on success, -1 otherwise.
*/
int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as);
/** load_image_targphys:
* Same as load_image_targphys_as(), but doesn't allow the caller to specify
* an AddressSpace.
@ -225,6 +237,25 @@ int rom_check_and_register_reset(void);
void rom_set_fw(FWCfgState *f);
void rom_set_order_override(int order);
void rom_reset_order_override(void);
/**
* rom_transaction_begin:
*
* Call this before of a series of rom_add_*() calls. Call
* rom_transaction_end() afterwards to commit or abort. These functions are
* useful for undoing a series of rom_add_*() calls if image file loading fails
* partway through.
*/
void rom_transaction_begin(void);
/**
* rom_transaction_end:
* @commit: true to commit added roms, false to drop added roms
*
* Call this after a series of rom_add_*() calls. See rom_transaction_begin().
*/
void rom_transaction_end(bool commit);
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
void *rom_ptr(hwaddr addr, size_t size);
void hmp_info_roms(Monitor *mon, const QDict *qdict);

4
include/hw/misc/aspeed_sdmc.h
View File

@ -14,7 +14,7 @@
#define TYPE_ASPEED_SDMC "aspeed.sdmc"
#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
#define ASPEED_SDMC_NR_REGS (0x8 >> 2)
#define ASPEED_SDMC_NR_REGS (0x174 >> 2)
typedef struct AspeedSDMCState {
/*< private >*/
@ -27,6 +27,8 @@ typedef struct AspeedSDMCState {
uint32_t silicon_rev;
uint32_t ram_bits;
uint64_t ram_size;
uint64_t max_ram_size;
uint32_t fixed_conf;
} AspeedSDMCState;

226
include/hw/misc/imx6ul_ccm.h Normal file
View File

@ -0,0 +1,226 @@
/*
* IMX6UL Clock Control Module
*
* Copyright (C) 2018 by Jean-Christophe Dubois <jcd@tribudubois.net>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef IMX6UL_CCM_H
#define IMX6UL_CCM_H
#include "hw/misc/imx_ccm.h"
#include "qemu/bitops.h"
#define CCM_CCR 0
#define CCM_CCDR 1
#define CCM_CSR 2
#define CCM_CCSR 3
#define CCM_CACRR 4
#define CCM_CBCDR 5
#define CCM_CBCMR 6
#define CCM_CSCMR1 7
#define CCM_CSCMR2 8
#define CCM_CSCDR1 9
#define CCM_CS1CDR 10
#define CCM_CS2CDR 11
#define CCM_CDCDR 12
#define CCM_CHSCCDR 13
#define CCM_CSCDR2 14
#define CCM_CSCDR3 15
#define CCM_CDHIPR 18
#define CCM_CTOR 20
#define CCM_CLPCR 21
#define CCM_CISR 22
#define CCM_CIMR 23
#define CCM_CCOSR 24
#define CCM_CGPR 25
#define CCM_CCGR0 26
#define CCM_CCGR1 27
#define CCM_CCGR2 28
#define CCM_CCGR3 29
#define CCM_CCGR4 30
#define CCM_CCGR5 31
#define CCM_CCGR6 32
#define CCM_CMEOR 34
#define CCM_MAX 35
#define CCM_ANALOG_PLL_ARM 0
#define CCM_ANALOG_PLL_ARM_SET 1
#define CCM_ANALOG_PLL_ARM_CLR 2
#define CCM_ANALOG_PLL_ARM_TOG 3
#define CCM_ANALOG_PLL_USB1 4
#define CCM_ANALOG_PLL_USB1_SET 5
#define CCM_ANALOG_PLL_USB1_CLR 6
#define CCM_ANALOG_PLL_USB1_TOG 7
#define CCM_ANALOG_PLL_USB2 8
#define CCM_ANALOG_PLL_USB2_SET 9
#define CCM_ANALOG_PLL_USB2_CLR 10
#define CCM_ANALOG_PLL_USB2_TOG 11
#define CCM_ANALOG_PLL_SYS 12
#define CCM_ANALOG_PLL_SYS_SET 13
#define CCM_ANALOG_PLL_SYS_CLR 14
#define CCM_ANALOG_PLL_SYS_TOG 15
#define CCM_ANALOG_PLL_SYS_SS 16
#define CCM_ANALOG_PLL_SYS_NUM 20
#define CCM_ANALOG_PLL_SYS_DENOM 24
#define CCM_ANALOG_PLL_AUDIO 28
#define CCM_ANALOG_PLL_AUDIO_SET 29
#define CCM_ANALOG_PLL_AUDIO_CLR 30
#define CCM_ANALOG_PLL_AUDIO_TOG 31
#define CCM_ANALOG_PLL_AUDIO_NUM 32
#define CCM_ANALOG_PLL_AUDIO_DENOM 36
#define CCM_ANALOG_PLL_VIDEO 40
#define CCM_ANALOG_PLL_VIDEO_SET 41
#define CCM_ANALOG_PLL_VIDEO_CLR 42
#define CCM_ANALOG_PLL_VIDEO_TOG 44
#define CCM_ANALOG_PLL_VIDEO_NUM 46
#define CCM_ANALOG_PLL_VIDEO_DENOM 48
#define CCM_ANALOG_PLL_ENET 56
#define CCM_ANALOG_PLL_ENET_SET 57
#define CCM_ANALOG_PLL_ENET_CLR 58
#define CCM_ANALOG_PLL_ENET_TOG 59
#define CCM_ANALOG_PFD_480 60
#define CCM_ANALOG_PFD_480_SET 61
#define CCM_ANALOG_PFD_480_CLR 62
#define CCM_ANALOG_PFD_480_TOG 63
#define CCM_ANALOG_PFD_528 64
#define CCM_ANALOG_PFD_528_SET 65
#define CCM_ANALOG_PFD_528_CLR 66
#define CCM_ANALOG_PFD_528_TOG 67
/* PMU registers */
#define PMU_REG_1P1 68
#define PMU_REG_3P0 72
#define PMU_REG_2P5 76
#define PMU_REG_CORE 80
#define CCM_ANALOG_MISC0 84
#define PMU_MISC0 CCM_ANALOG_MISC0
#define CCM_ANALOG_MISC0_SET 85
#define PMU_MISC0_SET CCM_ANALOG_MISC0_SET
#define CCM_ANALOG_MISC0_CLR 86
#define PMU_MISC0_CLR CCM_ANALOG_MISC0_CLR
#define CCM_ANALOG_MISC0_TOG 87
#define PMU_MISC0_TOG CCM_ANALOG_MISC0_TOG
#define CCM_ANALOG_MISC1 88
#define PMU_MISC1 CCM_ANALOG_MISC1
#define CCM_ANALOG_MISC1_SET 89
#define PMU_MISC1_SET CCM_ANALOG_MISC1_SET
#define CCM_ANALOG_MISC1_CLR 90
#define PMU_MISC1_CLR CCM_ANALOG_MISC1_CLR
#define CCM_ANALOG_MISC1_TOG 91
#define PMU_MISC1_TOG CCM_ANALOG_MISC1_TOG
#define CCM_ANALOG_MISC2 92
#define PMU_MISC2 CCM_ANALOG_MISC2
#define CCM_ANALOG_MISC2_SET 93
#define PMU_MISC2_SET CCM_ANALOG_MISC2_SET
#define CCM_ANALOG_MISC2_CLR 94
#define PMU_MISC2_CLR CCM_ANALOG_MISC2_CLR
#define CCM_ANALOG_MISC2_TOG 95
#define PMU_MISC2_TOG CCM_ANALOG_MISC2_TOG
#define TEMPMON_TEMPSENSE0 96
#define TEMPMON_TEMPSENSE0_SET 97
#define TEMPMON_TEMPSENSE0_CLR 98
#define TEMPMON_TEMPSENSE0_TOG 99
#define TEMPMON_TEMPSENSE1 100
#define TEMPMON_TEMPSENSE1_SET 101
#define TEMPMON_TEMPSENSE1_CLR 102
#define TEMPMON_TEMPSENSE1_TOG 103
#define TEMPMON_TEMPSENSE2 164
#define TEMPMON_TEMPSENSE2_SET 165
#define TEMPMON_TEMPSENSE2_CLR 166
#define TEMPMON_TEMPSENSE2_TOG 167
#define PMU_LOWPWR_CTRL 155
#define PMU_LOWPWR_CTRL_SET 156
#define PMU_LOWPWR_CTRL_CLR 157
#define PMU_LOWPWR_CTRL_TOG 158
#define USB_ANALOG_USB1_VBUS_DETECT 104
#define USB_ANALOG_USB1_VBUS_DETECT_SET 105
#define USB_ANALOG_USB1_VBUS_DETECT_CLR 106
#define USB_ANALOG_USB1_VBUS_DETECT_TOG 107
#define USB_ANALOG_USB1_CHRG_DETECT 108
#define USB_ANALOG_USB1_CHRG_DETECT_SET 109
#define USB_ANALOG_USB1_CHRG_DETECT_CLR 110
#define USB_ANALOG_USB1_CHRG_DETECT_TOG 111
#define USB_ANALOG_USB1_VBUS_DETECT_STAT 112
#define USB_ANALOG_USB1_CHRG_DETECT_STAT 116
#define USB_ANALOG_USB1_MISC 124
#define USB_ANALOG_USB1_MISC_SET 125
#define USB_ANALOG_USB1_MISC_CLR 126
#define USB_ANALOG_USB1_MISC_TOG 127
#define USB_ANALOG_USB2_VBUS_DETECT 128
#define USB_ANALOG_USB2_VBUS_DETECT_SET 129
#define USB_ANALOG_USB2_VBUS_DETECT_CLR 130
#define USB_ANALOG_USB2_VBUS_DETECT_TOG 131
#define USB_ANALOG_USB2_CHRG_DETECT 132
#define USB_ANALOG_USB2_CHRG_DETECT_SET 133
#define USB_ANALOG_USB2_CHRG_DETECT_CLR 134
#define USB_ANALOG_USB2_CHRG_DETECT_TOG 135
#define USB_ANALOG_USB2_VBUS_DETECT_STAT 136
#define USB_ANALOG_USB2_CHRG_DETECT_STAT 140
#define USB_ANALOG_USB2_MISC 148
#define USB_ANALOG_USB2_MISC_SET 149
#define USB_ANALOG_USB2_MISC_CLR 150
#define USB_ANALOG_USB2_MISC_TOG 151
#define USB_ANALOG_DIGPROG 152
#define CCM_ANALOG_MAX 4096
/* CCM_CBCMR */
#define R_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18)
#define R_CBCMR_PRE_PERIPH_CLK_SEL_LENGTH (2)
#define R_CBCMR_PERIPH_CLK2_SEL_SHIFT (12)
#define R_CBCMR_PERIPH_CLK2_SEL_LENGTH (2)
/* CCM_CBCDR */
#define R_CBCDR_AHB_PODF_SHIFT (10)
#define R_CBCDR_AHB_PODF_LENGTH (3)
#define R_CBCDR_IPG_PODF_SHIFT (8)
#define R_CBCDR_IPG_PODF_LENGTH (2)
#define R_CBCDR_PERIPH_CLK_SEL_SHIFT (25)
#define R_CBCDR_PERIPH_CLK_SEL_LENGTH (1)
#define R_CBCDR_PERIPH_CLK2_PODF_SHIFT (27)
#define R_CBCDR_PERIPH_CLK2_PODF_LENGTH (3)
/* CCM_CSCMR1 */
#define R_CSCMR1_PERCLK_PODF_SHIFT (0)
#define R_CSCMR1_PERCLK_PODF_LENGTH (6)
#define R_CSCMR1_PERCLK_CLK_SEL_SHIFT (6)
#define R_CSCMR1_PERCLK_CLK_SEL_LENGTH (1)
/* CCM_ANALOG_PFD_528 */
#define R_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0)
#define R_ANALOG_PFD_528_PFD0_FRAC_LENGTH (6)
#define R_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16)
#define R_ANALOG_PFD_528_PFD2_FRAC_LENGTH (6)
/* CCM_ANALOG_PLL_SYS */
#define R_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0)
#define R_ANALOG_PLL_SYS_DIV_SELECT_LENGTH (1)
#define CCM_ANALOG_PLL_LOCK (1 << 31);
#define TYPE_IMX6UL_CCM "imx6ul.ccm"
#define IMX6UL_CCM(obj) OBJECT_CHECK(IMX6ULCCMState, (obj), TYPE_IMX6UL_CCM)
typedef struct IMX6ULCCMState {
/* <private> */
IMXCCMState parent_obj;
/* <public> */
MemoryRegion container;
MemoryRegion ioccm;
MemoryRegion ioanalog;
uint32_t ccm[CCM_MAX];
uint32_t analog[CCM_ANALOG_MAX];
} IMX6ULCCMState;
#endif /* IMX6UL_CCM_H */

19
linux-user/syscall.c
View File

@ -10848,15 +10848,22 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
#endif
#ifdef TARGET_AARCH64
case TARGET_PR_SVE_SET_VL:
/* We cannot support either PR_SVE_SET_VL_ONEXEC
or PR_SVE_VL_INHERIT. Therefore, anything above
ARM_MAX_VQ results in EINVAL. */
/*
* We cannot support either PR_SVE_SET_VL_ONEXEC or
* PR_SVE_VL_INHERIT. Note the kernel definition
* of sve_vl_valid allows for VQ=512, i.e. VL=8192,
* even though the current architectural maximum is VQ=16.
*/
ret = -TARGET_EINVAL;
if (arm_feature(cpu_env, ARM_FEATURE_SVE)
&& arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) {
&& arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
CPUARMState *env = cpu_env;
int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
int vq = MAX(arg2 / 16, 1);
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t vq, old_vq;
old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
vq = MAX(arg2 / 16, 1);
vq = MIN(vq, cpu->sve_max_vq);
if (vq < old_vq) {
aarch64_sve_narrow_vq(env, vq);

17
target/arm/cpu.c
View File

@ -168,9 +168,9 @@ static void arm_cpu_reset(CPUState *s)
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
env->cp15.cptr_el[3] |= CPTR_EZ;
/* with maximum vector length */
env->vfp.zcr_el[1] = ARM_MAX_VQ - 1;
env->vfp.zcr_el[2] = ARM_MAX_VQ - 1;
env->vfp.zcr_el[3] = ARM_MAX_VQ - 1;
env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
#else
/* Reset into the highest available EL */
if (arm_feature(env, ARM_FEATURE_EL3)) {
@ -1255,6 +1255,15 @@ static void arm11mpcore_initfn(Object *obj)
cpu->reset_auxcr = 1;
}
static void cortex_m0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_M);
cpu->midr = 0x410cc200;
}
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@ -1845,6 +1854,8 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "arm1136", .initfn = arm1136_initfn },
{ .name = "arm1176", .initfn = arm1176_initfn },
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m0", .initfn = cortex_m0_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,

5
target/arm/cpu.h
View File

@ -857,6 +857,9 @@ struct ARMCPU {
/* Used to synchronize KVM and QEMU in-kernel device levels */
uint8_t device_irq_level;
/* Used to set the maximum vector length the cpu will support. */
uint32_t sve_max_vq;
};
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
@ -1266,7 +1269,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
* we store the underlying state in fpscr and just mask on read/write.
*/
#define FPSR_MASK 0xf800009f
#define FPCR_MASK 0x07f79f00
#define FPCR_MASK 0x07ff9f00
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */

29
target/arm/cpu64.c
View File

@ -29,6 +29,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "qapi/visitor.h"
static inline void set_feature(CPUARMState *env, int feature)
{
@ -217,6 +218,29 @@ static void aarch64_a53_initfn(Object *obj)
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
}
static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
}
static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
Error *err = NULL;
visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
error_setg(&err, "unsupported SVE vector length");
error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
ARM_MAX_VQ);
}
error_propagate(errp, err);
}
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
* otherwise, a CPU with as many features enabled as our emulation supports.
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@ -253,6 +277,10 @@ static void aarch64_max_initfn(Object *obj)
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
#endif
cpu->sve_max_vq = ARM_MAX_VQ;
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
}
}
@ -405,6 +433,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
uint64_t pmask;
assert(vq >= 1 && vq <= ARM_MAX_VQ);
assert(vq <= arm_env_get_cpu(env)->sve_max_vq);
/* Zap the high bits of the zregs. */
for (i = 0; i < 32; i++) {

18
target/arm/helper.c
View File

@ -11312,9 +11312,13 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
| (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
i = get_float_exception_flags(&env->vfp.fp_status);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
i |= get_float_exception_flags(&env->vfp.fp_status_f16);
/* FZ16 does not generate an input denormal exception. */
i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
& ~float_flag_input_denormal);
fpscr |= vfp_exceptbits_from_host(i);
return fpscr;
}
@ -11349,6 +11353,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
int i;
uint32_t changed;
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
val &= ~FPCR_FZ16;
}
changed = env->vfp.xregs[ARM_VFP_FPSCR];
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
env->vfp.vec_len = (val >> 16) & 7;
@ -12437,9 +12446,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
zcr_len = 0;
} else {
int current_el = arm_current_el(env);
ARMCPU *cpu = arm_env_get_cpu(env);
zcr_len = env->vfp.zcr_el[current_el <= 1 ? 1 : current_el];
zcr_len &= 0xf;
zcr_len = cpu->sve_max_vq - 1;
if (current_el <= 1) {
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
}
if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
}

4
target/arm/sve_helper.c
View File

@ -3358,7 +3358,7 @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
e2 = *(uint16_t *)(vm + H1_2(i));
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
*(uint16_t *)(vd + H1_2(i)) = r;
}
} while (i & 63);
@ -4045,7 +4045,7 @@ DO_LD1(sve_ld1bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, )
DO_LD1(sve_ld1bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, )
DO_LD1(sve_ld1hsu_r, cpu_lduw_data_ra, uint32_t, uint16_t, H1_4)
DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int8_t, H1_4)
DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int16_t, H1_4)
DO_LD1(sve_ld1hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, )
DO_LD1(sve_ld1hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, )

120
target/arm/translate-a64.c
View File

@ -137,14 +137,13 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
int el = arm_current_el(env);
const char *ns_status;
cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
env->pc, env->xregs[31]);
for (i = 0; i < 31; i++) {
cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
if ((i % 4) == 3) {
cpu_fprintf(f, "\n");
cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
for (i = 0; i < 32; i++) {
if (i == 31) {
cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
} else {
cpu_fprintf(f, " ");
cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
(i + 2) % 3 ? " " : "\n");
}
}
@ -153,8 +152,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
} else {
ns_status = "";
}
cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
cpu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
psr,
psr & PSTATE_N ? 'N' : '-',
psr & PSTATE_Z ? 'Z' : '-',
@ -164,17 +162,89 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
el,
psr & PSTATE_SP ? 'h' : 't');
if (flags & CPU_DUMP_FPU) {
int numvfpregs = 32;
for (i = 0; i < numvfpregs; i++) {
uint64_t *q = aa64_vfp_qreg(env, i);
uint64_t vlo = q[0];
uint64_t vhi = q[1];
cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c",
i, vhi, vlo, (i & 1 ? '\n' : ' '));
if (!(flags & CPU_DUMP_FPU)) {
cpu_fprintf(f, "\n");
return;
}
cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
vfp_get_fpcr(env), vfp_get_fpsr(env));
if (arm_feature(env, ARM_FEATURE_SVE)) {
int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */
for (i = 0; i <= FFR_PRED_NUM; i++) {
bool eol;
if (i == FFR_PRED_NUM) {
cpu_fprintf(f, "FFR=");
/* It's last, so end the line. */
eol = true;
} else {
cpu_fprintf(f, "P%02d=", i);
switch (zcr_len) {
case 0:
eol = i % 8 == 7;
break;
case 1:
eol = i % 6 == 5;
break;
case 2:
case 3:
eol = i % 3 == 2;
break;
default:
/* More than one quadword per predicate. */
eol = true;
break;
}
}
for (j = zcr_len / 4; j >= 0; j--) {
int digits;
if (j * 4 + 4 <= zcr_len + 1) {
digits = 16;
} else {
digits = (zcr_len % 4 + 1) * 4;
}
cpu_fprintf(f, "%0*" PRIx64 "%s", digits,
env->vfp.pregs[i].p[j],
j ? ":" : eol ? "\n" : " ");
}
}
for (i = 0; i < 32; i++) {
if (zcr_len == 0) {
cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
i, env->vfp.zregs[i].d[1],
env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
} else if (zcr_len == 1) {
cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
":%016" PRIx64 ":%016" PRIx64 "\n",
i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
} else {
for (j = zcr_len; j >= 0; j--) {
bool odd = (zcr_len - j) % 2 != 0;
if (j == zcr_len) {
cpu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
} else if (!odd) {
if (j > 0) {
cpu_fprintf(f, " [%x-%x]=", j, j - 1);
} else {
cpu_fprintf(f, " [%x]=", j);
}
}
cpu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
env->vfp.zregs[i].d[j * 2 + 1],
env->vfp.zregs[i].d[j * 2],
odd || j == 0 ? "\n" : ":");
}
}
}
} else {
for (i = 0; i < 32; i++) {
uint64_t *q = aa64_vfp_qreg(env, i);
cpu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
i, q[1], q[0], (i & 1 ? "\n" : " "));
}
cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
vfp_get_fpcr(env), vfp_get_fpsr(env));
}
}
@ -11353,12 +11423,12 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
feature = ARM_FEATURE_V8_DOTPROD;
break;
case 0x8: /* FCMLA, #0 */
case 0x9: /* FCMLA, #90 */
case 0xa: /* FCMLA, #180 */
case 0xb: /* FCMLA, #270 */
case 0xc: /* FCADD, #90 */
case 0xe: /* FCADD, #270 */
case 0x18: /* FCMLA, #0 */
case 0x19: /* FCMLA, #90 */
case 0x1a: /* FCMLA, #180 */
case 0x1b: /* FCMLA, #270 */
case 0x1c: /* FCADD, #90 */
case 0x1e: /* FCADD, #270 */
if (size == 0
|| (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
|| (size == 3 && !is_q)) {

30
target/arm/translate-sve.c
View File

@ -4093,7 +4093,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
}
static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
@ -4103,7 +4103,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
}
static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
@ -4372,12 +4372,11 @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
* The load should begin at the address Rn + IMM.
*/
static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
int rn, int imm)
static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
{
uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
uint32_t len_remain = len % 8;
uint32_t nparts = len / 8 + ctpop8(len_remain);
int len_align = QEMU_ALIGN_DOWN(len, 8);
int len_remain = len % 8;
int nparts = len / 8 + ctpop8(len_remain);
int midx = get_mem_index(s);
TCGv_i64 addr, t0, t1;
@ -4458,12 +4457,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
}
/* Similarly for stores. */
static void do_str(DisasContext *s, uint32_t vofs, uint32_t len,
int rn, int imm)
static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
{
uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
uint32_t len_remain = len % 8;
uint32_t nparts = len / 8 + ctpop8(len_remain);
int len_align = QEMU_ALIGN_DOWN(len, 8);
int len_remain = len % 8;
int nparts = len / 8 + ctpop8(len_remain);
int midx = get_mem_index(s);
TCGv_i64 addr, t0;
@ -4667,8 +4665,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
}
if (sve_access_check(s)) {
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_muli_i64(addr, cpu_reg(s, a->rm),
(a->nreg + 1) << dtype_msz(a->dtype));
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg);
}
@ -4821,6 +4818,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
unsigned vsz = vec_full_reg_size(s);
unsigned psz = pred_full_reg_size(s);
unsigned esz = dtype_esz[a->dtype];
unsigned msz = dtype_msz(a->dtype);
TCGLabel *over = gen_new_label();
TCGv_i64 temp;
@ -4844,7 +4842,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
/* Load the data. */
temp = tcg_temp_new_i64();
tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);
tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
s->be_data | dtype_mop[a->dtype]);
@ -4900,7 +4898,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn)
}
if (sve_access_check(s)) {
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz);
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz);
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg);
}

2
tests/Makefile.include
View File

@ -386,6 +386,7 @@ check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
gcov-files-arm-y += hw/timer/arm_mptimer.c
check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
check-qtest-arm-y += tests/sdhci-test$(EXESUF)
check-qtest-arm-y += tests/hexloader-test$(EXESUF)
check-qtest-aarch64-y = tests/numa-test$(EXESUF)
check-qtest-aarch64-y += tests/sdhci-test$(EXESUF)
@ -773,6 +774,7 @@ tests/qmp-test$(EXESUF): tests/qmp-test.o
tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o
tests/rtc-test$(EXESUF): tests/rtc-test.o
tests/m48t59-test$(EXESUF): tests/m48t59-test.o
tests/hexloader-test$(EXESUF): tests/hexloader-test.o
tests/endianness-test$(EXESUF): tests/endianness-test.o
tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y)
tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y)

18
tests/hex-loader-check-data/test.hex Normal file
View File

@ -0,0 +1,18 @@
:020000040001F9
:10000000000102030405060708090a0b0c0d0e0f78
:10001000101112131415161718191a1b1c1d1e1f68
:10002000202122232425262728292a2b2c2d2e2f58
:10003000303132333435363738393a3b3c3d3e3f48
:10004000404142434445464748494a4b4c4d4e4f38
:10005000505152535455565758595a5b5c5d5e5f28
:10006000606162636465666768696a6b6c6d6e6f18
:10007000707172737475767778797a7b7c7d7e7f08
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/*
* QTest testcase for the Intel Hexadecimal Object File Loader
*
* Authors:
* Su Hang <suhang16@mails.ucas.ac.cn> 2018
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
*/
#include "qemu/osdep.h"
#include "libqtest.h"
/* Load 'test.hex' and verify that the in-memory contents are as expected.
* 'test.hex' is a memory test pattern stored in Hexadecimal Object
* format. It loads at 0x10000 in RAM and contains values from 0 through
* 255.
*/
static void hex_loader_test(void)
{
unsigned int i;
const unsigned int base_addr = 0x00010000;
QTestState *s = qtest_initf(
"-M vexpress-a9 -nographic -device loader,file=tests/hex-loader-check-data/test.hex");
for (i = 0; i < 256; ++i) {
uint8_t val = qtest_readb(s, base_addr + i);
g_assert_cmpuint(i, ==, val);
}
qtest_quit(s);
}
int main(int argc, char **argv)
{
int ret;
g_test_init(&argc, &argv, NULL);
qtest_add_func("/tmp/hex_loader", hex_loader_test);
ret = g_test_run();
return ret;
}