Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1 contains both the base address of the encoded size (hashed) page tables. At present, we interpret the SDR1 value within the address translation path. But because the encodings of the size for 32-bit and 64-bit are different this makes for a confusing branch on the MMU type with a bunch of curly shifts and masks in the middle of the translate path. This patch cleans things up by moving the interpretation on SDR1 into the helper function handling the write to the register. This leaves a simple pre-sanitized base address and mask for the hash table in the CPUState structure which is easier to work with in the translation path. This makes the translation path more readable. It addresses the FIXME comment currently in the mtsdr1 helper, by validating the SDR1 value during interpretation. Finally it opens the way for emulating a pSeries-style partition where the hash table used for translation is not mapped into the guests's RAM. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
8500e3a912
commit
bb593904c1
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@ -3462,7 +3462,7 @@ static const MonitorDef monitor_defs[] = {
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{ "asr", offsetof(CPUState, asr) },
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#endif
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/* Segment registers */
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{ "sdr1", offsetof(CPUState, sdr1) },
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{ "sdr1", offsetof(CPUState, spr[SPR_SDR1]) },
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{ "sr0", offsetof(CPUState, sr[0]) },
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{ "sr1", offsetof(CPUState, sr[1]) },
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{ "sr2", offsetof(CPUState, sr[2]) },
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@ -359,6 +359,14 @@ union ppc_tlb_t {
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};
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#endif
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#define SDR_32_HTABORG 0xFFFF0000UL
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#define SDR_32_HTABMASK 0x000001FFUL
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#if defined(TARGET_PPC64)
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#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
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#define SDR_64_HTABSIZE 0x000000000000001FULL
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#endif /* defined(TARGET_PPC64 */
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typedef struct ppc_slb_t ppc_slb_t;
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struct ppc_slb_t {
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uint64_t esid;
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@ -642,7 +650,8 @@ struct CPUPPCState {
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int slb_nr;
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#endif
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/* segment registers */
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target_ulong sdr1;
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target_phys_addr_t htab_base;
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target_phys_addr_t htab_mask;
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target_ulong sr[32];
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/* BATs */
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int nb_BATs;
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@ -788,20 +788,19 @@ int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt)
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#endif /* defined(TARGET_PPC64) */
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/* Perform segment based translation */
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static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
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int sdr_sh,
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target_phys_addr_t hash,
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target_phys_addr_t mask)
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static inline target_phys_addr_t get_pgaddr(target_phys_addr_t htab_base,
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target_phys_addr_t htab_mask,
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target_phys_addr_t hash)
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{
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return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
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return htab_base | (hash & htab_mask);
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}
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static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
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target_phys_addr_t hash;
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target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
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int ds, vsid_sh, sdr_sh, pr, target_page_bits;
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int ds, vsid_sh, pr, target_page_bits;
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int ret, ret2;
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pr = msr_pr;
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@ -826,8 +825,6 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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ctx->eaddr = eaddr;
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vsid_mask = 0x00003FFFFFFFFF80ULL;
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vsid_sh = 7;
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sdr_sh = 18;
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sdr_mask = 0x3FF80;
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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@ -840,8 +837,6 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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vsid = sr & 0x00FFFFFF;
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vsid_mask = 0x01FFFFC0;
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vsid_sh = 6;
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sdr_sh = 16;
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sdr_mask = 0xFFC0;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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@ -857,29 +852,26 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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if (type != ACCESS_CODE || ctx->nx == 0) {
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/* Page address translation */
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/* Primary table address */
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sdr = env->sdr1;
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pgidx = (eaddr & page_mask) >> target_page_bits;
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
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/* XXX: this is false for 1 TB segments */
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hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
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} else
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#endif
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{
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htab_mask = sdr & 0x000001FF;
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hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
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}
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mask = (htab_mask << sdr_sh) | sdr_mask;
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LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
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" mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
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sdr, sdr_sh, hash, mask, page_mask);
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ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->pg_addr[0] = get_pgaddr(env->htab_base, env->htab_mask, hash);
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/* Secondary table address */
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hash = (~hash) & vsid_mask;
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LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
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" mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask);
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ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->pg_addr[1] = get_pgaddr(env->htab_base, env->htab_mask, hash);
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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/* Only 5 bits of the page index are used in the AVPN */
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@ -901,19 +893,22 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
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/* Software TLB search */
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ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
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} else {
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LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
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"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
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" pg_addr=" TARGET_FMT_plx "\n",
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sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx " pg_addr=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, pgidx, hash,
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ctx->pg_addr[0]);
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/* Primary table lookup */
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ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
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if (ret < 0) {
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/* Secondary table lookup */
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if (eaddr != 0xEFFFFFFF)
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LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
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"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
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" pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
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pgidx, hash, ctx->pg_addr[1]);
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx " pg_addr="
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TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, pgidx, hash,
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ctx->pg_addr[1]);
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ret2 = find_pte(env, ctx, 1, rw, type,
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target_page_bits);
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if (ret2 != -1)
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@ -1919,11 +1914,26 @@ void ppc_store_asr (CPUPPCState *env, target_ulong value)
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void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
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{
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LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
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if (env->sdr1 != value) {
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/* XXX: for PowerPC 64, should check that the HTABSIZE value
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* is <= 28
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*/
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env->sdr1 = value;
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if (env->spr[SPR_SDR1] != value) {
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env->spr[SPR_SDR1] = value;
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#if defined(TARGET_PPC64)
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if (env->mmu_model & POWERPC_MMU_64) {
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target_ulong htabsize = value & SDR_64_HTABSIZE;
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if (htabsize > 28) {
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fprintf(stderr, "Invalid HTABSIZE 0x" TARGET_FMT_lx
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" stored in SDR1\n", htabsize);
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htabsize = 28;
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}
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env->htab_mask = (1ULL << (htabsize + 18)) - 1;
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env->htab_base = value & SDR_64_HTABORG;
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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/* FIXME: Should check for valid HTABMASK values */
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env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF;
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env->htab_base = value & SDR_32_HTABORG;
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}
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tlb_flush(env, 1);
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}
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}
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@ -169,7 +169,7 @@ int kvm_arch_get_registers(CPUState *env)
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#ifdef KVM_CAP_PPC_SEGSTATE
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if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {
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env->sdr1 = sregs.u.s.sdr1;
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ppc_store_sdr1(env, sregs.u.s.sdr1);
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/* Sync SLB */
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#ifdef TARGET_PPC64
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@ -37,7 +37,7 @@ void cpu_save(QEMUFile *f, void *opaque)
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qemu_put_betls(f, &env->asr);
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qemu_put_sbe32s(f, &env->slb_nr);
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#endif
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qemu_put_betls(f, &env->sdr1);
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qemu_put_betls(f, &env->spr[SPR_SDR1]);
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for (i = 0; i < 32; i++)
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qemu_put_betls(f, &env->sr[i]);
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for (i = 0; i < 2; i++)
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@ -93,6 +93,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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{
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CPUState *env = (CPUState *)opaque;
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unsigned int i, j;
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target_ulong sdr1;
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for (i = 0; i < 32; i++)
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qemu_get_betls(f, &env->gpr[i]);
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@ -124,7 +125,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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qemu_get_betls(f, &env->asr);
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qemu_get_sbe32s(f, &env->slb_nr);
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#endif
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qemu_get_betls(f, &env->sdr1);
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qemu_get_betls(f, &sdr1);
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for (i = 0; i < 32; i++)
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qemu_get_betls(f, &env->sr[i]);
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for (i = 0; i < 2; i++)
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@ -152,6 +153,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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#endif
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for (i = 0; i < 1024; i++)
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qemu_get_betls(f, &env->spr[i]);
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ppc_store_sdr1(env, sdr1);
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qemu_get_be32s(f, &env->vscr);
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qemu_get_be64s(f, &env->spe_acc);
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qemu_get_be32s(f, &env->spe_fscr);
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@ -9126,7 +9126,7 @@ void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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#if !defined(CONFIG_USER_ONLY)
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cpu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " SDR1 "
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TARGET_FMT_lx "\n", env->spr[SPR_SRR0], env->spr[SPR_SRR1],
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env->sdr1);
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env->spr[SPR_SDR1]);
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#endif
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#undef RGPL
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@ -343,11 +343,6 @@ static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
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}
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/* SDR1 */
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static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
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}
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static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
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{
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gen_helper_store_sdr1(cpu_gpr[gprn]);
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@ -671,7 +666,7 @@ static void gen_spr_ne_601 (CPUPPCState *env)
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/* Memory management */
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spr_register(env, SPR_SDR1, "SDR1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_sdr1, &spr_write_sdr1,
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&spr_read_generic, &spr_write_sdr1,
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0x00000000);
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}
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