target/mips: MXU: Add handlers for max/min instructions
Add translation handlers for six max/min MXU instructions. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Aleksandar Markovic
parent
b621f0187e
commit
bb84cbf385
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@ -24823,6 +24823,282 @@ static void gen_mxu_S32XOR(DisasContext *ctx)
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}
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/*
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* MXU instruction category max/min
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* S32MAX D16MAX Q8MAX
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* S32MIN D16MIN Q8MIN
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*/
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/*
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* S32MAX XRa, XRb, XRc
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* Update XRa with the maximum of signed 32-bit integers contained
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* in XRb and XRc.
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*
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* S32MIN XRa, XRb, XRc
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* Update XRa with the minimum of signed 32-bit integers contained
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* in XRb and XRc.
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*
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------+---------+-----+-------+-------+-------+-----------+
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* | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
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* +-----------+---------+-----+-------+-------+-------+-----------+
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*/
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static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx)
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{
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uint32_t pad, opc, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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opc = extract32(ctx->opcode, 18, 3);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
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} else if (unlikely((XRb == 0) || (XRc == 0))) {
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/* exactly one operand is zero register - find which one is not...*/
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uint32_t XRx = XRb ? XRb : XRc;
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/* ...and do max/min operation with one operand 0 */
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if (opc == OPC_MXU_S32MAX) {
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tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
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} else {
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tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
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}
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} else if (unlikely(XRb == XRc)) {
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/* both operands same -> just set destination to one of them */
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tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
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} else {
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/* the most general case */
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if (opc == OPC_MXU_S32MAX) {
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tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1],
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mxu_gpr[XRc - 1]);
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} else {
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tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1],
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mxu_gpr[XRc - 1]);
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}
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}
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}
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/*
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* D16MAX
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* Update XRa with the 16-bit-wise maximums of signed integers
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* contained in XRb and XRc.
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*
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* D16MIN
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* Update XRa with the 16-bit-wise minimums of signed integers
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* contained in XRb and XRc.
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*
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------+---------+-----+-------+-------+-------+-----------+
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* | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
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* +-----------+---------+-----+-------+-------+-------+-----------+
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*/
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static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
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{
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uint32_t pad, opc, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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opc = extract32(ctx->opcode, 18, 3);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRc == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRa == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0);
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} else if (unlikely((XRb == 0) || (XRa == 0))) {
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/* exactly one operand is zero register - find which one is not...*/
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uint32_t XRx = XRb ? XRb : XRc;
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/* ...and do half-word-wise max/min with one operand 0 */
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TCGv_i32 t0 = tcg_temp_new();
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TCGv_i32 t1 = tcg_const_i32(0);
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/* the left half-word first */
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tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
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if (opc == OPC_MXU_D16MAX) {
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tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
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} else {
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tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
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}
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/* the right half-word */
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tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF);
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/* move half-words to the leftmost position */
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tcg_gen_shli_i32(t0, t0, 16);
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/* t0 will be max/min of t0 and t1 */
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if (opc == OPC_MXU_D16MAX) {
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tcg_gen_smax_i32(t0, t0, t1);
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} else {
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tcg_gen_smin_i32(t0, t0, t1);
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}
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/* return resulting half-words to its original position */
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tcg_gen_shri_i32(t0, t0, 16);
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/* finaly update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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} else if (unlikely(XRb == XRc)) {
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/* both operands same -> just set destination to one of them */
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tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
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} else {
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/* the most general case */
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TCGv_i32 t0 = tcg_temp_new();
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TCGv_i32 t1 = tcg_temp_new();
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/* the left half-word first */
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tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000);
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tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000);
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if (opc == OPC_MXU_D16MAX) {
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tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
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} else {
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tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
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}
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/* the right half-word */
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tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF);
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tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF);
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/* move half-words to the leftmost position */
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tcg_gen_shli_i32(t0, t0, 16);
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tcg_gen_shli_i32(t1, t1, 16);
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/* t0 will be max/min of t0 and t1 */
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if (opc == OPC_MXU_D16MAX) {
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tcg_gen_smax_i32(t0, t0, t1);
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} else {
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tcg_gen_smin_i32(t0, t0, t1);
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}
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/* return resulting half-words to its original position */
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tcg_gen_shri_i32(t0, t0, 16);
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/* finaly update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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}
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}
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/*
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* Q8MAX
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* Update XRa with the 8-bit-wise maximums of signed integers
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* contained in XRb and XRc.
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*
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* Q8MIN
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* Update XRa with the 8-bit-wise minimums of signed integers
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* contained in XRb and XRc.
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*
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------+---------+-----+-------+-------+-------+-----------+
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* | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
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* +-----------+---------+-----+-------+-------+-------+-----------+
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*/
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static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
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{
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uint32_t pad, opc, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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opc = extract32(ctx->opcode, 18, 3);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
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} else if (unlikely((XRb == 0) || (XRc == 0))) {
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/* exactly one operand is zero register - make it be the first...*/
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uint32_t XRx = XRb ? XRb : XRc;
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/* ...and do byte-wise max/min with one operand 0 */
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TCGv_i32 t0 = tcg_temp_new();
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TCGv_i32 t1 = tcg_const_i32(0);
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int32_t i;
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/* the leftmost byte (byte 3) first */
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tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000);
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if (opc == OPC_MXU_Q8MAX) {
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tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
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} else {
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tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
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}
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/* bytes 2, 1, 0 */
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for (i = 2; i >= 0; i--) {
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/* extract the byte */
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tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i));
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/* move the byte to the leftmost position */
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tcg_gen_shli_i32(t0, t0, 8 * (3 - i));
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/* t0 will be max/min of t0 and t1 */
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if (opc == OPC_MXU_Q8MAX) {
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tcg_gen_smax_i32(t0, t0, t1);
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} else {
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tcg_gen_smin_i32(t0, t0, t1);
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}
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/* return resulting byte to its original position */
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tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
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/* finaly update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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}
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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} else if (unlikely(XRb == XRc)) {
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/* both operands same -> just set destination to one of them */
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tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
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} else {
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/* the most general case */
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TCGv_i32 t0 = tcg_temp_new();
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TCGv_i32 t1 = tcg_temp_new();
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int32_t i;
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/* the leftmost bytes (bytes 3) first */
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tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000);
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tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000);
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if (opc == OPC_MXU_Q8MAX) {
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tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1);
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} else {
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tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1);
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}
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/* bytes 2, 1, 0 */
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for (i = 2; i >= 0; i--) {
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/* extract corresponding bytes */
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tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF << (8 * i));
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tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF << (8 * i));
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/* move the bytes to the leftmost position */
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tcg_gen_shli_i32(t0, t0, 8 * (3 - i));
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tcg_gen_shli_i32(t1, t1, 8 * (3 - i));
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/* t0 will be max/min of t0 and t1 */
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if (opc == OPC_MXU_Q8MAX) {
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tcg_gen_smax_i32(t0, t0, t1);
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} else {
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tcg_gen_smin_i32(t0, t0, t1);
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}
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/* return resulting byte to its original position */
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tcg_gen_shri_i32(t0, t0, 8 * (3 - i));
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/* finaly update the destination */
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tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
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}
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tcg_temp_free(t1);
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tcg_temp_free(t0);
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}
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}
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/*
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* Decoding engine for MXU
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* =======================
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@ -24844,34 +25120,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx)
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switch (opcode) {
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case OPC_MXU_S32MAX:
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/* TODO: Implement emulation of S32MAX instruction. */
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MIPS_INVAL("OPC_MXU_S32MAX");
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generate_exception_end(ctx, EXCP_RI);
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break;
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case OPC_MXU_S32MIN:
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/* TODO: Implement emulation of S32MIN instruction. */
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MIPS_INVAL("OPC_MXU_S32MIN");
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generate_exception_end(ctx, EXCP_RI);
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gen_mxu_S32MAX_S32MIN(ctx);
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break;
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case OPC_MXU_D16MAX:
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/* TODO: Implement emulation of D16MAX instruction. */
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MIPS_INVAL("OPC_MXU_D16MAX");
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generate_exception_end(ctx, EXCP_RI);
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break;
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case OPC_MXU_D16MIN:
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/* TODO: Implement emulation of D16MIN instruction. */
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MIPS_INVAL("OPC_MXU_D16MIN");
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generate_exception_end(ctx, EXCP_RI);
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gen_mxu_D16MAX_D16MIN(ctx);
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break;
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case OPC_MXU_Q8MAX:
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/* TODO: Implement emulation of Q8MAX instruction. */
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MIPS_INVAL("OPC_MXU_Q8MAX");
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generate_exception_end(ctx, EXCP_RI);
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break;
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case OPC_MXU_Q8MIN:
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/* TODO: Implement emulation of Q8MIN instruction. */
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MIPS_INVAL("OPC_MXU_Q8MIN");
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generate_exception_end(ctx, EXCP_RI);
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gen_mxu_Q8MAX_Q8MIN(ctx);
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break;
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case OPC_MXU_Q8SLT:
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/* TODO: Implement emulation of Q8SLT instruction. */
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