target/arm: Use mte_checkN for sve unpredicated stores
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4432,10 +4432,12 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
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int len_remain = len % 8;
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int nparts = len / 8 + ctpop8(len_remain);
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int midx = get_mem_index(s);
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TCGv_i64 addr, t0;
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TCGv_i64 dirty_addr, clean_addr, t0;
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addr = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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dirty_addr = tcg_temp_new_i64();
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tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm);
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clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8);
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tcg_temp_free_i64(dirty_addr);
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/* Note that unpredicated load/store of vector/predicate registers
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* are defined as a stream of bytes, which equates to little-endian
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@ -4448,33 +4450,35 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
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if (nparts <= 4) {
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int i;
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t0 = tcg_temp_new_i64();
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for (i = 0; i < len_align; i += 8) {
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tcg_gen_ld_i64(t0, cpu_env, vofs + i);
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tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i);
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tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEQ);
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tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
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tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
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}
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tcg_temp_free_i64(t0);
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} else {
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TCGLabel *loop = gen_new_label();
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TCGv_ptr t2, i = tcg_const_local_ptr(0);
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TCGv_ptr tp, i = tcg_const_local_ptr(0);
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/* Copy the clean address into a local temp, live across the loop. */
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t0 = clean_addr;
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clean_addr = tcg_temp_local_new_i64();
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tcg_gen_mov_i64(clean_addr, t0);
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tcg_temp_free_i64(t0);
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gen_set_label(loop);
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t2 = tcg_temp_new_ptr();
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tcg_gen_add_ptr(t2, cpu_env, i);
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tcg_gen_ld_i64(t0, t2, vofs);
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/* Minimize the number of local temps that must be re-read from
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* the stack each iteration. Instead, re-compute values other
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* than the loop counter.
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*/
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tcg_gen_addi_ptr(t2, i, imm);
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tcg_gen_extu_ptr_i64(addr, t2);
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tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn));
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tcg_temp_free_ptr(t2);
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tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEQ);
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t0 = tcg_temp_new_i64();
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tp = tcg_temp_new_ptr();
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tcg_gen_add_ptr(tp, cpu_env, i);
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tcg_gen_ld_i64(t0, tp, vofs);
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tcg_gen_addi_ptr(i, i, 8);
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tcg_temp_free_ptr(tp);
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tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
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tcg_gen_addi_i64(clean_addr, clean_addr, 8);
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tcg_temp_free_i64(t0);
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tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
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tcg_temp_free_ptr(i);
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@ -4482,29 +4486,30 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
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/* Predicate register stores can be any multiple of 2. */
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if (len_remain) {
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t0 = tcg_temp_new_i64();
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tcg_gen_ld_i64(t0, cpu_env, vofs + len_align);
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tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align);
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switch (len_remain) {
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case 2:
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case 4:
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case 8:
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tcg_gen_qemu_st_i64(t0, addr, midx, MO_LE | ctz32(len_remain));
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tcg_gen_qemu_st_i64(t0, clean_addr, midx,
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MO_LE | ctz32(len_remain));
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break;
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case 6:
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tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUL);
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tcg_gen_addi_i64(addr, addr, 4);
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tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL);
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tcg_gen_addi_i64(clean_addr, clean_addr, 4);
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUW);
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tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW);
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break;
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default:
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g_assert_not_reached();
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}
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}
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tcg_temp_free_i64(addr);
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tcg_temp_free_i64(t0);
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}
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tcg_temp_free_i64(clean_addr);
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}
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static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
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