* target-cris/op.c: Make sure the bit-test insn only updates the XNZ flags.
* target-cris/helper.c: Update ERP for user-mode simulation aswell. * hw/etraxfs_timer.c: Support multiple timers. * hw/etraxfs_ser.c: Multiple ports, the data just goes to stdout. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4004 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
bffd92fed9
commit
bbaf29c769
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@ -26,23 +26,28 @@
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#include <ctype.h>
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#include "hw.h"
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#define RW_TR_DMA_EN 0xb0026004
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#define RW_DOUT 0xb002601c
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#define RW_STAT_DIN 0xb0026020
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#define R_STAT_DIN 0xb0026024
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#define D(x)
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#define RW_TR_DMA_EN 0x04
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#define RW_DOUT 0x1c
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#define RW_STAT_DIN 0x20
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#define R_STAT_DIN 0x24
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static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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CPUState *env;
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uint32_t r = 0;
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printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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env = opaque;
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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}
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static uint32_t ser_readw (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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CPUState *env;
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uint32_t r = 0;
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printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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env = opaque;
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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}
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@ -51,7 +56,7 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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CPUState *env = opaque;
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uint32_t r = 0;
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switch (addr)
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switch (addr & 0xfff)
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{
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case RW_TR_DMA_EN:
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break;
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@ -70,21 +75,23 @@ static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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static void
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ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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CPUState *env;
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env = opaque;
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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CPUState *env;
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env = opaque;
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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switch (addr)
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switch (addr & 0xfff)
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{
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case RW_TR_DMA_EN:
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break;
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@ -119,4 +126,7 @@ void etraxfs_ser_init(CPUState *env, qemu_irq *irqs)
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ser_regs = cpu_register_io_memory(0, ser_read, ser_write, env);
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cpu_register_physical_memory (0xb0026000, 0x3c, ser_regs);
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cpu_register_physical_memory (0xb0028000, 0x3c, ser_regs);
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cpu_register_physical_memory (0xb002a000, 0x3c, ser_regs);
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cpu_register_physical_memory (0xb002c000, 0x3c, ser_regs);
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}
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@ -26,6 +26,8 @@
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#include "hw.h"
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#include "qemu-timer.h"
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#define D(x)
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void etrax_ack_irq(CPUState *env, uint32_t mask);
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#define R_TIME 0xb001e038
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@ -54,9 +56,18 @@ struct fs_timer_t {
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CPUState *env;
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qemu_irq *irq;
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uint32_t mask;
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struct timeval last;
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};
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static struct fs_timer_t timer0;
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static struct fs_timer_t timer[2];
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static inline int timer_index(target_phys_addr_t addr)
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{
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int t = 0;
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if (addr >= 0xb005e000)
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t = 1;
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return t;
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}
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/* diff two timevals. Return a single int in us. */
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int diff_timeval_us(struct timeval *a, struct timeval *b)
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@ -71,16 +82,20 @@ int diff_timeval_us(struct timeval *a, struct timeval *b)
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static uint32_t timer_readb (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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CPUState *env;
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uint32_t r = 0;
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printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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env = opaque;
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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}
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static uint32_t timer_readw (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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CPUState *env;
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uint32_t r = 0;
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printf ("%s %x pc=%x\n", __func__, addr, env->pc);
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env = opaque;
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r;
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}
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@ -88,24 +103,25 @@ static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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uint32_t r = 0;
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int t = timer_index(addr);
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switch (addr) {
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case R_TMR0_DATA:
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break;
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case R_TMR1_DATA:
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printf ("R_TMR1_DATA\n");
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D(printf ("R_TMR1_DATA\n"));
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break;
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case R_TIME:
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{
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static struct timeval last;
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struct timeval now;
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gettimeofday(&now, NULL);
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if (!(last.tv_sec == 0 && last.tv_usec == 0)) {
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r = diff_timeval_us(&now, &last);
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if (!(timer[t].last.tv_sec == 0
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&& timer[t].last.tv_usec == 0)) {
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r = diff_timeval_us(&now, &timer[t].last);
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r *= 1000; /* convert to ns. */
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r++; /* make sure we increase for each call. */
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}
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last = now;
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timer[t].last = now;
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break;
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}
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@ -125,14 +141,16 @@ static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
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static void
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timer_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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CPUState *env;
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env = opaque;
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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timer_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
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CPUState *env;
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env = opaque;
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void write_ctrl(struct fs_timer_t *t, uint32_t v)
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@ -165,7 +183,7 @@ static void write_ctrl(struct fs_timer_t *t, uint32_t v)
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if (t->limit > 2048)
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{
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t->scale = 2048;
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ptimer_set_period(timer0.ptimer, freq_hz / t->scale);
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ptimer_set_period(t->ptimer, freq_hz / t->scale);
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}
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printf ("op=%d\n", op);
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@ -187,11 +205,11 @@ static void write_ctrl(struct fs_timer_t *t, uint32_t v)
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}
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}
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static void timer_ack_irq(void)
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static void timer_ack_irq(struct fs_timer_t *t)
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{
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if (!(r_intr & timer0.mask & rw_intr_mask)) {
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qemu_irq_lower(timer0.irq[0]);
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etrax_ack_irq(timer0.env, 1 << 0x1b);
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if (!(r_intr & t->mask & rw_intr_mask)) {
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qemu_irq_lower(t->irq[0]);
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etrax_ack_irq(t->env, 1 << 0x1b);
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}
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}
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@ -199,31 +217,33 @@ static void
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env = opaque;
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printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc);
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int t = timer_index(addr);
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D(printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc));
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switch (addr)
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{
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case RW_TMR0_DIV:
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printf ("RW_TMR0_DIV=%x\n", value);
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timer0.limit = value;
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D(printf ("RW_TMR0_DIV=%x\n", value));
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timer[t].limit = value;
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break;
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case RW_TMR0_CTRL:
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printf ("RW_TMR0_CTRL=%x\n", value);
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write_ctrl(&timer0, value);
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D(printf ("RW_TMR0_CTRL=%x\n", value));
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write_ctrl(&timer[t], value);
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break;
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case RW_TMR1_DIV:
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printf ("RW_TMR1_DIV=%x\n", value);
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D(printf ("RW_TMR1_DIV=%x\n", value));
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break;
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case RW_TMR1_CTRL:
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printf ("RW_TMR1_CTRL=%x\n", value);
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D(printf ("RW_TMR1_CTRL=%x\n", value));
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break;
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case RW_INTR_MASK:
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printf ("RW_INTR_MASK=%x\n", value);
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D(printf ("RW_INTR_MASK=%x\n", value));
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rw_intr_mask = value;
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break;
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case RW_ACK_INTR:
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r_intr &= ~value;
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timer_ack_irq();
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timer_ack_irq(&timer[t]);
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break;
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default:
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printf ("%s %x %x pc=%x\n",
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@ -247,7 +267,6 @@ static CPUWriteMemoryFunc *timer_write[] = {
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static void timer_irq(void *opaque)
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{
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struct fs_timer_t *t = opaque;
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r_intr |= t->mask;
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if (t->mask & rw_intr_mask) {
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qemu_irq_raise(t->irq[0]);
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@ -258,12 +277,19 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs)
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{
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int timer_regs;
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timer0.bh = qemu_bh_new(timer_irq, &timer0);
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timer0.ptimer = ptimer_init(timer0.bh);
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timer0.irq = irqs + 0x1b;
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timer0.mask = 1;
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timer0.env = env;
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timer[0].bh = qemu_bh_new(timer_irq, &timer[0]);
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timer[0].ptimer = ptimer_init(timer[0].bh);
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timer[0].irq = irqs + 0x1b;
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timer[0].mask = 1;
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timer[0].env = env;
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timer[1].bh = qemu_bh_new(timer_irq, &timer[1]);
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timer[1].ptimer = ptimer_init(timer[1].bh);
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timer[1].irq = irqs + 0x1b;
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timer[1].mask = 1;
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timer[1].env = env;
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timer_regs = cpu_register_io_memory(0, timer_read, timer_write, env);
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cpu_register_physical_memory (0xb001e000, 0x5c, timer_regs);
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cpu_register_physical_memory (0xb005e000, 0x5c, timer_regs);
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}
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@ -32,22 +32,23 @@
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void do_interrupt (CPUState *env)
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{
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env->exception_index = -1;
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env->exception_index = -1;
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env->pregs[PR_ERP] = env->pc;
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}
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int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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env->exception_index = 0xaa;
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env->debug1 = address;
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cpu_dump_state(env, stderr, fprintf, 0);
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printf("%s addr=%x env->pc=%x\n", __func__, address, env->pc);
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return 1;
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env->exception_index = 0xaa;
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env->debug1 = address;
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cpu_dump_state(env, stderr, fprintf, 0);
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env->pregs[PR_ERP] = env->pc;
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return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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{
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return addr;
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return addr;
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}
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#else /* !CONFIG_USER_ONLY */
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@ -61,7 +62,6 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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address &= TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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// printf ("%s pc=%x %x w=%d smmu=%d\n", __func__, env->pc, address, rw, is_softmmu);
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miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
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if (miss)
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{
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@ -73,7 +73,6 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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{
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phy = res.phy;
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}
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// printf ("a=%x phy=%x\n", address, phy);
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return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
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}
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@ -113,7 +112,6 @@ void do_interrupt(CPUState *env)
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break;
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case EXCP_MMU_MISS:
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// printf ("MMU miss\n");
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irqnum = 4;
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ebp = env->pregs[PR_EBP];
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isr = ldl_code(ebp + irqnum * 4);
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@ -967,6 +967,8 @@ void OPPROTO op_btst_T0_T1 (void)
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The N flag is set according to the selected bit in the dest reg.
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The Z flag is set if the selected bit and all bits to the right are
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zero.
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The X flag is cleared.
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Other flags are left untouched.
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The destination reg is not affected.*/
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unsigned int fz, sbit, bset, mask, masked_t0;
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@ -975,8 +977,11 @@ void OPPROTO op_btst_T0_T1 (void)
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mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
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masked_t0 = T0 & mask;
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fz = !(masked_t0 | bset);
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/* Clear the X, N and Z flags. */
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T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
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/* Set the N and Z flags accordingly. */
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T0 = (bset << 3) | (fz << 2);
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T0 |= (bset << 3) | (fz << 2);
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RETURN();
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}
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