From d06edeca2f26d33f5823e6ab883408dab6ef25dc Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Fri, 14 Aug 2020 22:14:38 +0900 Subject: [PATCH 1/8] elf: Add EM_RX definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RX's ELF machine is not defined in "elf.h". Added it. Signed-off-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20200814131438.28406-1-ysato@users.sourceforge.jp> Signed-off-by: Philippe Mathieu-Daudé --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index c117a4d1ab..d9bf4a95d8 100644 --- a/include/elf.h +++ b/include/elf.h @@ -172,6 +172,8 @@ typedef struct mips_elf_abiflags_v0 { #define EM_UNICORE32 110 /* UniCore32 */ +#define EM_RX 173 /* Renesas RX family */ + #define EM_RISCV 243 /* RISC-V */ #define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */ From 2f5af2dcf3cfd051e121fef2b861d46d113f1ac7 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 20 Oct 2020 17:39:33 +0200 Subject: [PATCH 2/8] hw/timer/sh_timer: Coding style clean-up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace TAB characters with spaces, put code after case-statement on separate lines and add some curly braces in related lines to keep checkpatch.pl happy. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201020153935.54315-2-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 89 +++++++++++++++++++++++++++++---------------- 1 file changed, 57 insertions(+), 32 deletions(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index bb0e1c8ee5..b09e30f938 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -117,35 +117,55 @@ static void sh_timer_write(void *opaque, hwaddr offset, case 2: freq >>= 6; break; case 3: freq >>= 8; break; case 4: freq >>= 10; break; - case 6: - case 7: if (s->feat & TIMER_FEAT_EXTCLK) break; - default: hw_error("sh_timer_write: Reserved TPSC value\n"); break; + case 6: + case 7: + if (s->feat & TIMER_FEAT_EXTCLK) { + break; + } + default: + hw_error("sh_timer_write: Reserved TPSC value\n"); + break; } switch ((value & TIMER_TCR_CKEG) >> 3) { - case 0: break; + case 0: + break; case 1: case 2: - case 3: if (s->feat & TIMER_FEAT_EXTCLK) break; - default: hw_error("sh_timer_write: Reserved CKEG value\n"); break; + case 3: + if (s->feat & TIMER_FEAT_EXTCLK) { + break; + } + default: + hw_error("sh_timer_write: Reserved CKEG value\n"); + break; } switch ((value & TIMER_TCR_ICPE) >> 6) { - case 0: break; + case 0: + break; case 2: - case 3: if (s->feat & TIMER_FEAT_CAPT) break; - default: hw_error("sh_timer_write: Reserved ICPE value\n"); break; + case 3: + if (s->feat & TIMER_FEAT_CAPT) { + break; + } + default: + hw_error("sh_timer_write: Reserved ICPE value\n"); + break; } - if ((value & TIMER_TCR_UNF) == 0) + if ((value & TIMER_TCR_UNF) == 0) { s->int_level = 0; + } - value &= ~TIMER_TCR_UNF; + value &= ~TIMER_TCR_UNF; - if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) + if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { hw_error("sh_timer_write: Reserved ICPF value\n"); + } - value &= ~TIMER_TCR_ICPF; /* capture not supported */ + value &= ~TIMER_TCR_ICPF; /* capture not supported */ - if (value & TIMER_TCR_RESERVED) + if (value & TIMER_TCR_RESERVED) { hw_error("sh_timer_write: Reserved TCR bits set\n"); + } s->tcr = value; ptimer_set_limit(s->timer, s->tcor, 0); ptimer_set_freq(s->timer, freq); @@ -158,8 +178,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, case OFFSET_TCPR: if (s->feat & TIMER_FEAT_CAPT) { s->tcpr = value; - break; - } + break; + } default: hw_error("sh_timer_write: Bad offset %x\n", (int)offset); } @@ -241,8 +261,9 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, #endif if (offset >= 0x20) { - if (!(s->feat & TMU012_FEAT_3CHAN)) - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + if (!(s->feat & TMU012_FEAT_3CHAN)) { + hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + } return sh_timer_read(s->timer[2], offset - 0x20); } @@ -272,33 +293,36 @@ static void tmu012_write(void *opaque, hwaddr offset, #endif if (offset >= 0x20) { - if (!(s->feat & TMU012_FEAT_3CHAN)) - hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + if (!(s->feat & TMU012_FEAT_3CHAN)) { + hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); + } sh_timer_write(s->timer[2], offset - 0x20, value); - return; + return; } if (offset >= 0x14) { sh_timer_write(s->timer[1], offset - 0x14, value); - return; + return; } if (offset >= 0x08) { sh_timer_write(s->timer[0], offset - 0x08, value); - return; + return; } if (offset == 4) { sh_timer_start_stop(s->timer[0], value & (1 << 0)); sh_timer_start_stop(s->timer[1], value & (1 << 1)); - if (s->feat & TMU012_FEAT_3CHAN) + if (s->feat & TMU012_FEAT_3CHAN) { sh_timer_start_stop(s->timer[2], value & (1 << 2)); - else - if (value & (1 << 2)) + } else { + if (value & (1 << 2)) { hw_error("tmu012_write: Bad channel\n"); + } + } - s->tstr = value; - return; + s->tstr = value; + return; } if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { @@ -314,8 +338,8 @@ static const MemoryRegionOps tmu012_ops = { void tmu012_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq, - qemu_irq ch0_irq, qemu_irq ch1_irq, - qemu_irq ch2_irq0, qemu_irq ch2_irq1) + qemu_irq ch0_irq, qemu_irq ch1_irq, + qemu_irq ch2_irq0, qemu_irq ch2_irq1) { tmu012_state *s; int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; @@ -324,9 +348,10 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base, s->feat = feat; s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); - if (feat & TMU012_FEAT_3CHAN) + if (feat & TMU012_FEAT_3CHAN) { s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, - ch2_irq0); /* ch2_irq1 not supported */ + ch2_irq0); /* ch2_irq1 not supported */ + } memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, "timer", 0x100000000ULL); From 97edd8ba4b167b6adfbda9598280e5b31270fd40 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 20 Oct 2020 17:39:34 +0200 Subject: [PATCH 3/8] hw/timer/sh_timer: Silence warnings about missing fallthrough statements MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When compiling with -Werror=implicit-fallthrough, gcc complains about missing fallthrough annotations in this file. Looking at the code, the fallthrough is very likely intended here, so add some comments to silence the compiler warnings. Fixes: cd1a3f6840e ("Stand-alone TMU emulation code") Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201020153935.54315-3-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index b09e30f938..934daaa7dc 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -122,6 +122,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, if (s->feat & TIMER_FEAT_EXTCLK) { break; } + /* fallthrough */ default: hw_error("sh_timer_write: Reserved TPSC value\n"); break; @@ -135,6 +136,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, if (s->feat & TIMER_FEAT_EXTCLK) { break; } + /* fallthrough */ default: hw_error("sh_timer_write: Reserved CKEG value\n"); break; @@ -147,6 +149,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, if (s->feat & TIMER_FEAT_CAPT) { break; } + /* fallthrough */ default: hw_error("sh_timer_write: Reserved ICPE value\n"); break; @@ -180,6 +183,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, s->tcpr = value; break; } + /* fallthrough */ default: hw_error("sh_timer_write: Bad offset %x\n", (int)offset); } From 45514b48df9d46478b10929cdfe1b74f01dceb99 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 20 Oct 2020 17:39:35 +0200 Subject: [PATCH 4/8] hw/timer/sh_timer: Remove superfluous "break" statements MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit hw_error() is marked as QEMU_NORETURN, so the "break" statements after this function are just dead code. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201020153935.54315-4-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/sh_timer.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 934daaa7dc..58af1a1edb 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -125,7 +125,6 @@ static void sh_timer_write(void *opaque, hwaddr offset, /* fallthrough */ default: hw_error("sh_timer_write: Reserved TPSC value\n"); - break; } switch ((value & TIMER_TCR_CKEG) >> 3) { case 0: @@ -139,7 +138,6 @@ static void sh_timer_write(void *opaque, hwaddr offset, /* fallthrough */ default: hw_error("sh_timer_write: Reserved CKEG value\n"); - break; } switch ((value & TIMER_TCR_ICPE) >> 6) { case 0: @@ -152,7 +150,6 @@ static void sh_timer_write(void *opaque, hwaddr offset, /* fallthrough */ default: hw_error("sh_timer_write: Reserved ICPE value\n"); - break; } if ((value & TIMER_TCR_UNF) == 0) { s->int_level = 0; From 02b8e735c16d50e2108621a4af283989b38f508b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 27 Oct 2020 00:13:00 +0100 Subject: [PATCH 5/8] target/sh4: Update coding style to make checkpatch.pl happy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid checkpatch.pl warnings in the next commit. Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/op_helper.c | 8 +++++--- target/sh4/translate.c | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 14c3db0f48..fcd9ac7271 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -398,9 +398,11 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0) /* "Approximate" 1/sqrt(x) via actual computation. */ t0 = float32_sqrt(t0, &env->fp_status); t0 = float32_div(float32_one, t0, &env->fp_status); - /* Since this is supposed to be an approximation, an imprecision - exception is required. One supposes this also follows the usual - IEEE rule that other exceptions take precidence. */ + /* + * Since this is supposed to be an approximation, an imprecision + * exception is required. One supposes this also follows the usual + * IEEE rule that other exceptions take precidence. + */ if (get_float_exception_flags(&env->fp_status) == 0) { set_float_exception_flags(float_flag_inexact, &env->fp_status); } diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 60c863d9e1..ec5b04889e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1959,9 +1959,11 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) NEXT_INSN; switch (ctx->opcode & 0xf00f) { case 0x6003: /* mov Rm,Rn */ - /* Here we want to recognize ld_dst being saved for later consumtion, - or for another input register being copied so that ld_dst need not - be clobbered during the operation. */ + /* + * Here we want to recognize ld_dst being saved for later consumtion, + * or for another input register being copied so that ld_dst need not + * be clobbered during the operation. + */ op_dst = B11_8; mv_src = B7_4; if (op_dst == ld_dst) { From 23b5d9fa099aa2fcd89869a4fc581a26c63edb1a Mon Sep 17 00:00:00 2001 From: Lichang Zhao Date: Fri, 9 Oct 2020 14:44:44 +0800 Subject: [PATCH 6/8] target/sh4: fix some comment spelling errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are many spelling errors in the comments of target/sh4. Use spellcheck to check the spelling errors, then fix them. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude Message-Id: <20201009064449.2336-10-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.h | 2 +- target/sh4/op_helper.c | 2 +- target/sh4/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dbe58c7888..714e3b5641 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -160,7 +160,7 @@ typedef struct CPUSH4State { uint32_t pteh; /* page table entry high register */ uint32_t ptel; /* page table entry low register */ uint32_t ptea; /* page table entry assistance register */ - uint32_t ttb; /* tranlation table base register */ + uint32_t ttb; /* translation table base register */ uint32_t tea; /* TLB exception address register */ uint32_t tra; /* TRAPA exception register */ uint32_t expevt; /* exception event register */ diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index fcd9ac7271..c0cbb95382 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -401,7 +401,7 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0) /* * Since this is supposed to be an approximation, an imprecision * exception is required. One supposes this also follows the usual - * IEEE rule that other exceptions take precidence. + * IEEE rule that other exceptions take precedence. */ if (get_float_exception_flags(&env->fp_status) == 0) { set_float_exception_flags(float_flag_inexact, &env->fp_status); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index ec5b04889e..9312790623 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1960,7 +1960,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) switch (ctx->opcode & 0xf00f) { case 0x6003: /* mov Rm,Rn */ /* - * Here we want to recognize ld_dst being saved for later consumtion, + * Here we want to recognize ld_dst being saved for later consumption, * or for another input register being copied so that ld_dst need not * be clobbered during the operation. */ From 9784143808a0692adf98578e4ba89170c83da354 Mon Sep 17 00:00:00 2001 From: Lichang Zhao Date: Fri, 9 Oct 2020 14:44:39 +0800 Subject: [PATCH 7/8] target/rx: Fix some comment spelling errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are many spelling errors in the comments of target/rx. Use spellcheck to check the spelling errors, then fix them. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude Message-Id: <20201009064449.2336-5-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé --- target/rx/op_helper.c | 2 +- target/rx/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index f89d294f2b..59389f4992 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz) env->psw_c = (tmp <= env->regs[2]); } -/* accumlator operations */ +/* accumulator operations */ void helper_rmpa(CPURXState *env, uint32_t sz) { uint64_t result_l, prev; diff --git a/target/rx/translate.c b/target/rx/translate.c index 482278edd2..9ea941c630 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_xor_i32(temp, arg1, arg2); tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); tcg_temp_free_i32(temp); - /* CMP not requred return */ + /* CMP not required return */ if (ret) { tcg_gen_mov_i32(ret, cpu_psw_s); } From 81c76433407a1c5b5560a3b8fb593671667e9b13 Mon Sep 17 00:00:00 2001 From: Chetan Pant Date: Fri, 23 Oct 2020 12:38:40 +0000 Subject: [PATCH 8/8] target/rx: Fix Lesser GPL version number MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20201023123840.19988-1-chetan4windows@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- target/rx/insns.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/insns.decode b/target/rx/insns.decode index 232a61fc8e..ca9334b37a 100644 --- a/target/rx/insns.decode +++ b/target/rx/insns.decode @@ -7,7 +7,7 @@ # This library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public # License as published by the Free Software Foundation; either -# version 2 of the License, or (at your option) any later version. +# version 2.1 of the License, or (at your option) any later version. # # This library is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of