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tests/tcg/xtensa: clean up test set

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Drop test_fail: we know that exit simcall works. Now that it's not run
automatically there's no point in keeping it.
Drop test_pipeline: we're not modeling pipeline, we don't control ccount
and there's no plan to do so.
Enable test_boolean: it won't break on cores without boolean option, it
will do testing on cores with boolean option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-03-22 12:49:17 -07:00
parent 393cf60bf7
commit bc19449acc
3 changed files with 1 additions and 167 deletions
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2
tests/tcg/xtensa/Makefile.softmmu-target
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@ -8,7 +8,7 @@ XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa
XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S))
XTENSA_TESTS = $(patsubst $(XTENSA_SRC)/%.S, %, $(XTENSA_ALL))
# Filter out common blobs and broken tests
XTENSA_BROKEN_TESTS = crt vectors test_boolean test_pipeline test_fail
XTENSA_BROKEN_TESTS = crt vectors
XTENSA_USABLE_TESTS = $(filter-out $(XTENSA_BROKEN_TESTS), $(XTENSA_TESTS))
# add to the list of tests

9
tests/tcg/xtensa/test_fail.S
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@ -1,9 +0,0 @@
#include "macros.inc"
test_suite fail
test fail
test_fail
test_end
test_suite_end

157
tests/tcg/xtensa/test_pipeline.S
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@ -1,157 +0,0 @@
#include "macros.inc"
.purgem test
.macro test name
movi a2, 1f
movi a3, 99f
0:
ipf a2, 0
ipf a2, 4
ipf a2, 8
ipf a2, 12
addi a2, a2, 16
blt a2, a3, 0b
j 1f
.align 4
1:
.endm
test_suite pipeline
test register_no_stall
rsr a3, ccount
add a5, a6, a6
add a6, a5, a5
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 3
test_end
test register_stall
l32i a5, a1, 0 /* data cache preload */
nop
rsr a3, ccount
l32i a5, a1, 0
add a6, a5, a5 /* M-to-E interlock */
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 4
test_end
test j0_stall
rsr a3, ccount
j 1f /* E + 2-cycle penalty */
1:
rsr a4, ccount /* E */
sub a3, a4, a3
assert eqi, a3, 4
test_end
test j1_stall
rsr a3, ccount
j 1f
nop
1:
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 4
test_end
test j5_stall
rsr a3, ccount
j 1f
nop
nop
nop
nop
nop
1:
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 4
test_end
test b_no_stall
movi a5, 1
rsr a3, ccount
beqi a5, 2, 1f
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 2
1:
test_end
test b1_stall
movi a5, 1
rsr a3, ccount
beqi a5, 1, 1f
nop
1:
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 4
test_end
test b5_stall
movi a5, 1
rsr a3, ccount
beqi a5, 1, 1f
nop
nop
nop
nop
nop
1:
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 4
test_end
/* PS *SYNC */
test ps_dsync
rsr a5, ps
isync
rsr a3, ccount
wsr a5, ps
dsync
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 5
test_end
test ps_esync
rsr a5, ps
isync
rsr a3, ccount
wsr a5, ps
esync
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 5
test_end
test ps_rsync
rsr a5, ps
isync
rsr a3, ccount
wsr a5, ps
rsync
rsr a4, ccount
sub a3, a4, a3
assert eqi, a3, 5
test_end
test ps_isync
rsr a5, ps
isync
rsr a3, ccount
wsr a5, ps
isync
rsr a4, ccount
sub a3, a4, a3
movi a4, 9
assert eq, a3, a4
test_end
test_suite_end