intel_iommu: avoid unnamed fields
Also avoid unnamed fields for portability. Also, rename VTD_IRTE to VTD_IR_TableEntry for coding style compliance. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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1a210f631b
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bc38ee10fc
@ -2010,7 +2010,7 @@ static Property vtd_properties[] = {
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/* Read IRTE entry with specific index */
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static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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VTD_IRTE *entry, uint16_t sid)
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VTD_IR_TableEntry *entry, uint16_t sid)
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{
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static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
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{0xffff, 0xfffb, 0xfff9, 0xfff8};
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@ -2026,7 +2026,7 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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return -VTD_FR_IR_ROOT_INVAL;
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}
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if (!entry->present) {
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if (!entry->irte.present) {
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VTD_DPRINTF(GENERAL, "error: present flag not set in IRTE"
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" entry index %u value 0x%"PRIx64 " 0x%"PRIx64,
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index, le64_to_cpu(entry->data[1]),
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@ -2034,8 +2034,8 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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return -VTD_FR_IR_ENTRY_P;
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}
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if (entry->__reserved_0 || entry->__reserved_1 || \
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entry->__reserved_2) {
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if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
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entry->irte.__reserved_2) {
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VTD_DPRINTF(GENERAL, "error: IRTE entry index %"PRIu16
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" reserved fields non-zero: 0x%"PRIx64 " 0x%"PRIx64,
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index, le64_to_cpu(entry->data[1]),
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@ -2045,14 +2045,14 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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if (sid != X86_IOMMU_SID_INVALID) {
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/* Validate IRTE SID */
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source_id = le32_to_cpu(entry->source_id);
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switch (entry->sid_vtype) {
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source_id = le32_to_cpu(entry->irte.source_id);
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switch (entry->irte.sid_vtype) {
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case VTD_SVT_NONE:
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VTD_DPRINTF(IR, "No SID validation for IRTE index %d", index);
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break;
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case VTD_SVT_ALL:
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mask = vtd_svt_mask[entry->sid_q];
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mask = vtd_svt_mask[entry->irte.sid_q];
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if ((source_id & mask) != (sid & mask)) {
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VTD_DPRINTF(GENERAL, "SID validation for IRTE index "
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"%d failed (reqid 0x%04x sid 0x%04x)", index,
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@ -2075,7 +2075,7 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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default:
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VTD_DPRINTF(GENERAL, "Invalid SVT bits (0x%x) in IRTE index "
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"%d", entry->sid_vtype, index);
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"%d", entry->irte.sid_vtype, index);
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/* Take this as verification failure. */
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return -VTD_FR_IR_SID_ERR;
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break;
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@ -2089,7 +2089,7 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
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VTDIrq *irq, uint16_t sid)
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{
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VTD_IRTE irte = {};
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VTD_IR_TableEntry irte = {};
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int ret = 0;
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ret = vtd_irte_get(iommu, index, &irte, sid);
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@ -2097,18 +2097,18 @@ static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
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return ret;
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}
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irq->trigger_mode = irte.trigger_mode;
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irq->vector = irte.vector;
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irq->delivery_mode = irte.delivery_mode;
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irq->dest = le32_to_cpu(irte.dest_id);
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irq->trigger_mode = irte.irte.trigger_mode;
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irq->vector = irte.irte.vector;
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irq->delivery_mode = irte.irte.delivery_mode;
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irq->dest = le32_to_cpu(irte.irte.dest_id);
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if (!iommu->intr_eime) {
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#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
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#define VTD_IR_APIC_DEST_SHIFT (8)
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irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
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VTD_IR_APIC_DEST_SHIFT;
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}
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irq->dest_mode = irte.dest_mode;
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irq->redir_hint = irte.redir_hint;
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irq->dest_mode = irte.irte.dest_mode;
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irq->redir_hint = irte.irte.redir_hint;
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VTD_DPRINTF(IR, "remapping interrupt index %d: trig:%u,vec:%u,"
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"deliver:%u,dest:%u,dest_mode:%u", index,
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@ -2167,23 +2167,23 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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}
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addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
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if (le16_to_cpu(addr.__head) != 0xfee) {
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if (le16_to_cpu(addr.addr.__head) != 0xfee) {
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VTD_DPRINTF(GENERAL, "error: MSI addr low 32 bits invalid: "
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"0x%"PRIx32, addr.data);
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return -VTD_FR_IR_REQ_RSVD;
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}
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/* This is compatible mode. */
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if (addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
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if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
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goto do_not_translate;
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}
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index = addr.index_h << 15 | le16_to_cpu(addr.index_l);
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index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
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#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
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#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
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if (addr.sub_valid) {
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if (addr.addr.sub_valid) {
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/* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
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index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
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}
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@ -2193,7 +2193,7 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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return ret;
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}
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if (addr.sub_valid) {
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if (addr.addr.sub_valid) {
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VTD_DPRINTF(IR, "received MSI interrupt");
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if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
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VTD_DPRINTF(GENERAL, "error: MSI data bits non-zero for "
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@ -2217,7 +2217,7 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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* We'd better keep the last two bits, assuming that guest OS
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* might modify it. Keep it does not hurt after all.
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*/
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irq.msi_addr_last_bits = addr.__not_care;
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irq.msi_addr_last_bits = addr.addr.__not_care;
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/* Translate VTDIrq to MSI message */
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vtd_generate_msi_message(&irq, translated);
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@ -59,7 +59,7 @@ typedef struct IntelIOMMUState IntelIOMMUState;
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typedef struct VTDAddressSpace VTDAddressSpace;
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typedef struct VTDIOTLBEntry VTDIOTLBEntry;
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typedef struct VTDBus VTDBus;
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typedef union VTD_IRTE VTD_IRTE;
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typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
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typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
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typedef struct VTDIrq VTDIrq;
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typedef struct VTD_MSIMessage VTD_MSIMessage;
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@ -120,7 +120,7 @@ enum {
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};
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/* Interrupt Remapping Table Entry Definition */
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union VTD_IRTE {
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union VTD_IR_TableEntry {
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struct {
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#ifdef HOST_WORDS_BIGENDIAN
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uint32_t dest_id:32; /* Destination ID */
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@ -159,7 +159,7 @@ union VTD_IRTE {
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uint64_t sid_vtype:2; /* Source-ID Validation Type */
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uint64_t __reserved_2:44; /* Reserved 2 */
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#endif
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} QEMU_PACKED;
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} QEMU_PACKED irte;
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uint64_t data[2];
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};
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@ -184,7 +184,7 @@ union VTD_IR_MSIAddress {
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uint32_t index_l:15; /* Interrupt index bit 14-0 */
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uint32_t __head:12; /* Should always be: 0x0fee */
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#endif
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} QEMU_PACKED;
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} QEMU_PACKED addr;
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uint32_t data;
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};
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