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target-i386: Implement BLSR, BLSMSK, BLSI 

Do all of group 17 at one time for ease.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-01-23 16:44:37 -08:00
parent c7ab7565bc
commit bc4b43dc2f
5 changed files with 95 additions and 1 deletions
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18
target-i386/cc_helper.c
View File

@ -155,6 +155,13 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
case CC_OP_SARL:
return compute_all_sarl(dst, src1);
case CC_OP_BMILGB:
return compute_all_bmilgb(dst, src1);
case CC_OP_BMILGW:
return compute_all_bmilgw(dst, src1);
case CC_OP_BMILGL:
return compute_all_bmilgl(dst, src1);
#ifdef TARGET_X86_64
case CC_OP_MULQ:
return compute_all_mulq(dst, src1);
@ -176,6 +183,8 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
return compute_all_shlq(dst, src1);
case CC_OP_SARQ:
return compute_all_sarq(dst, src1);
case CC_OP_BMILGQ:
return compute_all_bmilgq(dst, src1);
#endif
}
}
@ -254,6 +263,13 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
case CC_OP_SHLL:
return compute_c_shll(dst, src1);
case CC_OP_BMILGB:
return compute_c_bmilgb(dst, src1);
case CC_OP_BMILGW:
return compute_c_bmilgw(dst, src1);
case CC_OP_BMILGL:
return compute_c_bmilgl(dst, src1);
#ifdef TARGET_X86_64
case CC_OP_ADDQ:
return compute_c_addq(dst, src1);
@ -265,6 +281,8 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
return compute_c_sbbq(dst, src1, src2);
case CC_OP_SHLQ:
return compute_c_shlq(dst, src1);
case CC_OP_BMILGQ:
return compute_c_bmilgq(dst, src1);
#endif
}
}

18
target-i386/cc_helper_template.h
View File

@ -217,6 +217,24 @@ static int glue(compute_all_mul, SUFFIX)(DATA_TYPE dst, target_long src1)
return cf | pf | af | zf | sf | of;
}
static int glue(compute_all_bmilg, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
{
int cf, pf, af, zf, sf, of;
cf = (src1 == 0);
pf = 0; /* undefined */
af = 0; /* undefined */
zf = (dst == 0) * CC_Z;
sf = lshift(dst, 8 - DATA_BITS) & CC_S;
of = 0;
return cf | pf | af | zf | sf | of;
}
static int glue(compute_c_bmilg, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
{
return src1 == 0;
}
#undef DATA_BITS
#undef SIGN_MASK
#undef DATA_TYPE

5
target-i386/cpu.h
View File

@ -636,6 +636,11 @@ typedef enum {
CC_OP_SARL,
CC_OP_SARQ,
CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
CC_OP_BMILGW,
CC_OP_BMILGL,
CC_OP_BMILGQ,
CC_OP_NB,
} CCOp;

7
target-i386/helper.c
View File

@ -55,7 +55,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env)
/***********************************************************/
/* x86 debug */
static const char *cc_op_str[] = {
static const char *cc_op_str[CC_OP_NB] = {
"DYNAMIC",
"EFLAGS",
@ -108,6 +108,11 @@ static const char *cc_op_str[] = {
"SARW",
"SARL",
"SARQ",
"BMILGB",
"BMILGW",
"BMILGL",
"BMILGQ",
};
static void

48
target-i386/translate.c
View File

@ -209,6 +209,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = {
[CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC,
};
static void set_cc_op(DisasContext *s, CCOp op)
@ -988,6 +989,11 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
return (CCPrepare) { .cond = TCG_COND_NE,
.reg = cpu_cc_src, .mask = -1 };
case CC_OP_BMILGB ... CC_OP_BMILGQ:
size = s->cc_op - CC_OP_BMILGB;
t0 = gen_ext_tl(reg, cpu_cc_src, size, false);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
case CC_OP_EFLAGS:
case CC_OP_SARB ... CC_OP_SARQ:
/* CC_SRC & 1 */
@ -4066,6 +4072,48 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
}
break;
case 0x0f3:
case 0x1f3:
case 0x2f3:
case 0x3f3: /* Group 17 */
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1)
|| !(s->prefix & PREFIX_VEX)
|| s->vex_l != 0) {
goto illegal_op;
}
ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (reg & 7) {
case 1: /* blsr By,Ey */
tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
gen_op_mov_reg_T0(ot, s->vex_v);
gen_op_update2_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 2: /* blsmsk By,Ey */
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
case 3: /* blsi By, Ey */
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_subi_tl(cpu_T[0], cpu_T[0], 1);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
set_cc_op(s, CC_OP_BMILGB + ot);
break;
default:
goto illegal_op;
}
break;
default:
goto illegal_op;
}