target/ppc: fix helper_xvmadd* argument order
When the xsmadd* insns were moved to decodetree, the helper arguments
were reordered to better match the PowerISA description. The same macro
is used to declare xvmadd* helpers, but the translation macro of these
insns was not changed accordingly.
Reported-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Fixes: e4318ab2e4
("target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20220325111851.718966-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -1324,31 +1324,31 @@ TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO)
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#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr xt, xa, b, c; \
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TCGv_ptr xt, s1, s2, s3; \
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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xt = gen_vsr_ptr(xT(ctx->opcode)); \
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xa = gen_vsr_ptr(xA(ctx->opcode)); \
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s1 = gen_vsr_ptr(xA(ctx->opcode)); \
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if (ctx->opcode & PPC_BIT32(25)) { \
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/* \
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* AxT + B \
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*/ \
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b = gen_vsr_ptr(xT(ctx->opcode)); \
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c = gen_vsr_ptr(xB(ctx->opcode)); \
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s2 = gen_vsr_ptr(xB(ctx->opcode)); \
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s3 = gen_vsr_ptr(xT(ctx->opcode)); \
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} else { \
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/* \
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* AxB + T \
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*/ \
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b = gen_vsr_ptr(xB(ctx->opcode)); \
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c = gen_vsr_ptr(xT(ctx->opcode)); \
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s2 = gen_vsr_ptr(xT(ctx->opcode)); \
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s3 = gen_vsr_ptr(xB(ctx->opcode)); \
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} \
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gen_helper_##name(cpu_env, xt, xa, b, c); \
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gen_helper_##name(cpu_env, xt, s1, s2, s3); \
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tcg_temp_free_ptr(xt); \
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tcg_temp_free_ptr(xa); \
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tcg_temp_free_ptr(b); \
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tcg_temp_free_ptr(c); \
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tcg_temp_free_ptr(s1); \
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tcg_temp_free_ptr(s2); \
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tcg_temp_free_ptr(s3); \
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}
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GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
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