target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()
All of the callers of get_phys_addr() and arm_tlb_fill() now ignore the FSR values they return, so we can just remove the argument entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Stefano Stabellini <sstabellini@kernel.org> Message-id: 1512503192-2239-12-git-send-email-peter.maydell@linaro.org
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@ -28,7 +28,7 @@ typedef struct ARMCacheAttrs {
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static bool get_phys_addr(CPUARMState *env, target_ulong address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
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target_ulong *page_size, uint32_t *fsr,
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target_ulong *page_size,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
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static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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@ -2160,7 +2160,6 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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hwaddr phys_addr;
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target_ulong page_size;
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int prot;
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uint32_t fsr_unused;
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bool ret;
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uint64_t par64;
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MemTxAttrs attrs = {};
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@ -2168,7 +2167,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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ARMCacheAttrs cacheattrs = {};
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ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
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&prot, &page_size, &fsr_unused, &fi, &cacheattrs);
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&prot, &page_size, &fi, &cacheattrs);
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/* TODO: this is not the correct condition to use to decide whether
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* to report a PAR in 64-bit or 32-bit format.
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*/
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@ -6981,7 +6980,6 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
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target_ulong page_size;
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hwaddr physaddr;
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int prot;
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uint32_t fsr;
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v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
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if (!sattrs.nsc || sattrs.ns) {
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@ -6995,7 +6993,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
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return false;
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}
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if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx,
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&physaddr, &attrs, &prot, &page_size, &fsr, &fi, NULL)) {
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&physaddr, &attrs, &prot, &page_size, &fi, NULL)) {
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/* the MPU lookup failed */
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env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
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armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
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@ -9749,14 +9747,13 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
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* @attrs: set to the memory transaction attributes to use
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* @prot: set to the permissions for the page containing phys_ptr
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* @page_size: set to the size of the page containing phys_ptr
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* @fsr: set to the DFSR/IFSR value on failure
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* @fi: set to fault info if the translation fails
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* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
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*/
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static bool get_phys_addr(CPUARMState *env, target_ulong address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
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target_ulong *page_size, uint32_t *fsr,
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target_ulong *page_size,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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{
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if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
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@ -9771,7 +9768,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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ret = get_phys_addr(env, address, access_type,
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stage_1_mmu_idx(mmu_idx), &ipa, attrs,
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prot, page_size, fsr, fi, cacheattrs);
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prot, page_size, fi, cacheattrs);
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/* If S1 fails or S2 is disabled, return early. */
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if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
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@ -9784,7 +9781,6 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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phys_ptr, attrs, &s2_prot,
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page_size, fi,
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cacheattrs != NULL ? &cacheattrs2 : NULL);
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*fsr = arm_fi_to_lfsc(fi);
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fi->s2addr = ipa;
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/* Combine the S1 and S2 perms. */
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*prot &= s2_prot;
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@ -9830,17 +9826,14 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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/* PMSAv8 */
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ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
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phys_ptr, attrs, prot, fi);
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*fsr = arm_fi_to_sfsc(fi);
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} else if (arm_feature(env, ARM_FEATURE_V7)) {
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/* PMSAv7 */
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ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
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phys_ptr, prot, fi);
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*fsr = arm_fi_to_sfsc(fi);
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} else {
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/* Pre-v7 MPU */
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ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
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phys_ptr, prot, fi);
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*fsr = arm_fi_to_sfsc(fi);
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}
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qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
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" mmu_idx %u -> %s (prot %c%c%c)\n",
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@ -9866,24 +9859,15 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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}
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if (regime_using_lpae_format(env, mmu_idx)) {
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bool ret = get_phys_addr_lpae(env, address, access_type, mmu_idx,
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phys_ptr, attrs, prot, page_size,
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fi, cacheattrs);
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*fsr = arm_fi_to_lfsc(fi);
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return ret;
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return get_phys_addr_lpae(env, address, access_type, mmu_idx,
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phys_ptr, attrs, prot, page_size,
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fi, cacheattrs);
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} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
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bool ret = get_phys_addr_v6(env, address, access_type, mmu_idx,
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phys_ptr, attrs, prot, page_size, fi);
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*fsr = arm_fi_to_sfsc(fi);
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return ret;
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return get_phys_addr_v6(env, address, access_type, mmu_idx,
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phys_ptr, attrs, prot, page_size, fi);
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} else {
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bool ret = get_phys_addr_v5(env, address, access_type, mmu_idx,
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return get_phys_addr_v5(env, address, access_type, mmu_idx,
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phys_ptr, prot, page_size, fi);
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*fsr = arm_fi_to_sfsc(fi);
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return ret;
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}
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}
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@ -9892,7 +9876,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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* fsr with ARM DFSR/IFSR fault register format value on failure.
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*/
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bool arm_tlb_fill(CPUState *cs, vaddr address,
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MMUAccessType access_type, int mmu_idx, uint32_t *fsr,
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MMUAccessType access_type, int mmu_idx,
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ARMMMUFaultInfo *fi)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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@ -9905,7 +9889,7 @@ bool arm_tlb_fill(CPUState *cs, vaddr address,
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ret = get_phys_addr(env, address, access_type,
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core_to_arm_mmu_idx(env, mmu_idx), &phys_addr,
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&attrs, &prot, &page_size, fsr, fi, NULL);
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&attrs, &prot, &page_size, fi, NULL);
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if (!ret) {
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/* Map a single [sub]page. */
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phys_addr &= TARGET_PAGE_MASK;
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@ -9927,14 +9911,13 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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target_ulong page_size;
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int prot;
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bool ret;
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uint32_t fsr;
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ARMMMUFaultInfo fi = {};
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ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
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*attrs = (MemTxAttrs) {};
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ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
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attrs, &prot, &page_size, &fsr, &fi, NULL);
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attrs, &prot, &page_size, &fi, NULL);
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if (ret) {
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return -1;
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@ -690,7 +690,7 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
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/* Do a page table walk and add page to TLB if possible */
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bool arm_tlb_fill(CPUState *cpu, vaddr address,
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MMUAccessType access_type, int mmu_idx,
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uint32_t *fsr, ARMMMUFaultInfo *fi);
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ARMMMUFaultInfo *fi);
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/* Return true if the stage 1 translation regime is using LPAE format page
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* tables */
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@ -176,10 +176,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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bool ret;
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uint32_t fsr = 0;
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ARMMMUFaultInfo fi = {};
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ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi);
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ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi);
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if (unlikely(ret)) {
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ARMCPU *cpu = ARM_CPU(cs);
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