intel_iommu: convert dbg macros to traces for inv
VT-d codes are still using static DEBUG_INTEL_IOMMU macro. That's not good, and we should end the day when we need to recompile the code before getting useful debugging information for vt-d. Time to switch to the trace system. This is the first patch to do it. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Jason Wang <jasowang@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Peter Xu
Michael S. Tsirkin
parent
6e9055641b
commit
bc535e59c4
@ -35,6 +35,7 @@
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#include "sysemu/kvm.h"
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#include "hw/i386/apic_internal.h"
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#include "kvm_i386.h"
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#include "trace.h"
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/*#define DEBUG_INTEL_IOMMU*/
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#ifdef DEBUG_INTEL_IOMMU
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@ -474,22 +475,19 @@ static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
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/* Set the IWC field and try to generate an invalidation completion interrupt */
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static void vtd_generate_completion_event(IntelIOMMUState *s)
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{
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VTD_DPRINTF(INV, "completes an invalidation wait command with "
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"Interrupt Flag");
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if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
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VTD_DPRINTF(INV, "there is a previous interrupt condition to be "
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"serviced by software, "
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"new invalidation event is not generated");
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trace_vtd_inv_desc_wait_irq("One pending, skip current");
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return;
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}
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vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
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vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
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if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
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VTD_DPRINTF(INV, "IM filed in IECTL_REG is set, new invalidation "
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"event is not generated");
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trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
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"new event not generated");
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return;
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} else {
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/* Generate the interrupt event */
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trace_vtd_inv_desc_wait_irq("Generating complete event");
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vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
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vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
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}
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@ -923,6 +921,7 @@ static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
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static void vtd_context_global_invalidate(IntelIOMMUState *s)
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{
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trace_vtd_inv_desc_cc_global();
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s->context_cache_gen++;
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if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
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vtd_reset_context_cache(s);
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@ -962,9 +961,11 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
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uint16_t mask;
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VTDBus *vtd_bus;
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VTDAddressSpace *vtd_as;
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uint16_t devfn;
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uint8_t bus_n, devfn;
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uint16_t devfn_it;
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trace_vtd_inv_desc_cc_devices(source_id, func_mask);
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switch (func_mask & 3) {
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case 0:
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mask = 0; /* No bits in the SID field masked */
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@ -980,16 +981,16 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
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break;
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}
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mask = ~mask;
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VTD_DPRINTF(INV, "device-selective invalidation source 0x%"PRIx16
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" mask %"PRIu16, source_id, mask);
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vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
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bus_n = VTD_SID_TO_BUS(source_id);
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vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
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if (vtd_bus) {
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devfn = VTD_SID_TO_DEVFN(source_id);
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for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
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vtd_as = vtd_bus->dev_as[devfn_it];
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if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
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VTD_DPRINTF(INV, "invalidate context-cahce of devfn 0x%"PRIx16,
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devfn_it);
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trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
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VTD_PCI_FUNC(devfn_it));
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vtd_as->context_cache_entry.context_cache_gen = 0;
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}
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}
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@ -1302,9 +1303,7 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
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{
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if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
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(inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
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VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Invalidation "
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"Wait Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
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inv_desc->hi, inv_desc->lo);
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trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
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return false;
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}
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if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
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@ -1316,21 +1315,18 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
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/* FIXME: need to be masked with HAW? */
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dma_addr_t status_addr = inv_desc->hi;
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VTD_DPRINTF(INV, "status data 0x%x, status addr 0x%"PRIx64,
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status_data, status_addr);
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trace_vtd_inv_desc_wait_sw(status_addr, status_data);
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status_data = cpu_to_le32(status_data);
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if (dma_memory_write(&address_space_memory, status_addr, &status_data,
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sizeof(status_data))) {
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VTD_DPRINTF(GENERAL, "error: fail to perform a coherent write");
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trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo);
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return false;
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}
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} else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
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/* Interrupt flag */
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VTD_DPRINTF(INV, "Invalidation Wait Descriptor interrupt completion");
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vtd_generate_completion_event(s);
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} else {
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VTD_DPRINTF(GENERAL, "error: invalid Invalidation Wait Descriptor: "
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"hi 0x%"PRIx64 " lo 0x%"PRIx64, inv_desc->hi, inv_desc->lo);
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trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
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return false;
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}
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return true;
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@ -1339,30 +1335,29 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
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static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
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VTDInvDesc *inv_desc)
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{
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uint16_t sid, fmask;
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if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
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VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Context-cache "
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"Invalidate Descriptor");
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trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
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return false;
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}
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switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
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case VTD_INV_DESC_CC_DOMAIN:
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VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
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(uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
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trace_vtd_inv_desc_cc_domain(
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(uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
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/* Fall through */
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case VTD_INV_DESC_CC_GLOBAL:
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VTD_DPRINTF(INV, "global invalidation");
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vtd_context_global_invalidate(s);
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break;
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case VTD_INV_DESC_CC_DEVICE:
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vtd_context_device_invalidate(s, VTD_INV_DESC_CC_SID(inv_desc->lo),
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VTD_INV_DESC_CC_FM(inv_desc->lo));
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sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
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fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
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vtd_context_device_invalidate(s, sid, fmask);
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break;
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default:
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VTD_DPRINTF(GENERAL, "error: invalid granularity in Context-cache "
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"Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
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inv_desc->hi, inv_desc->lo);
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trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
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return false;
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}
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return true;
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@ -1376,22 +1371,19 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
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if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
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(inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
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VTD_DPRINTF(GENERAL, "error: non-zero reserved field in IOTLB "
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"Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
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inv_desc->hi, inv_desc->lo);
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trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
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return false;
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}
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switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
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case VTD_INV_DESC_IOTLB_GLOBAL:
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VTD_DPRINTF(INV, "global invalidation");
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trace_vtd_inv_desc_iotlb_global();
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vtd_iotlb_global_invalidate(s);
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break;
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case VTD_INV_DESC_IOTLB_DOMAIN:
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domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
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VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
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domain_id);
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trace_vtd_inv_desc_iotlb_domain(domain_id);
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vtd_iotlb_domain_invalidate(s, domain_id);
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break;
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@ -1399,20 +1391,16 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
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domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
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addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
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am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
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VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
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" addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
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trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am);
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if (am > VTD_MAMV) {
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VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
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"%"PRIu8, (uint8_t)VTD_MAMV);
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trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
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return false;
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}
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vtd_iotlb_page_invalidate(s, domain_id, addr, am);
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break;
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default:
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VTD_DPRINTF(GENERAL, "error: invalid granularity in IOTLB Invalidate "
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"Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
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inv_desc->hi, inv_desc->lo);
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trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
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return false;
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}
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return true;
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@ -1511,33 +1499,28 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
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switch (desc_type) {
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case VTD_INV_DESC_CC:
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VTD_DPRINTF(INV, "Context-cache Invalidate Descriptor hi 0x%"PRIx64
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" lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
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trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo);
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if (!vtd_process_context_cache_desc(s, &inv_desc)) {
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return false;
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}
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break;
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case VTD_INV_DESC_IOTLB:
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VTD_DPRINTF(INV, "IOTLB Invalidate Descriptor hi 0x%"PRIx64
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" lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
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trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo);
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if (!vtd_process_iotlb_desc(s, &inv_desc)) {
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return false;
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}
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break;
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case VTD_INV_DESC_WAIT:
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VTD_DPRINTF(INV, "Invalidation Wait Descriptor hi 0x%"PRIx64
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" lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
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trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
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if (!vtd_process_wait_desc(s, &inv_desc)) {
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return false;
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}
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break;
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case VTD_INV_DESC_IEC:
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VTD_DPRINTF(INV, "Invalidation Interrupt Entry Cache "
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"Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
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inv_desc.hi, inv_desc.lo);
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trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo);
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if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
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return false;
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}
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@ -1552,9 +1535,7 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
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break;
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default:
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VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type "
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"hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8,
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inv_desc.hi, inv_desc.lo, desc_type);
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trace_vtd_inv_desc_invalid(inv_desc.hi, inv_desc.lo);
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return false;
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}
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s->iq_head++;
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@ -3,6 +3,24 @@
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# hw/i386/x86-iommu.c
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x86_iommu_iec_notify(bool global, uint32_t index, uint32_t mask) "Notify IEC invalidation: global=%d index=%" PRIu32 " mask=%" PRIu32
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# hw/i386/intel_iommu.c
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vtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "Device %02x:%02x.%x switching address space (iommu enabled=%d)"
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vtd_inv_desc(const char *type, uint64_t hi, uint64_t lo) "invalidate desc type %s high 0x%"PRIx64" low 0x%"PRIx64
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vtd_inv_desc_invalid(uint64_t hi, uint64_t lo) "invalid inv desc hi 0x%"PRIx64" lo 0x%"PRIx64
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vtd_inv_desc_cc_domain(uint16_t domain) "context invalidate domain 0x%"PRIx16
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vtd_inv_desc_cc_global(void) "context invalidate globally"
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vtd_inv_desc_cc_device(uint8_t bus, uint8_t dev, uint8_t fn) "context invalidate device %02"PRIx8":%02"PRIx8".%02"PRIx8
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vtd_inv_desc_cc_devices(uint16_t sid, uint16_t fmask) "context invalidate devices sid 0x%"PRIx16" fmask 0x%"PRIx16
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vtd_inv_desc_cc_invalid(uint64_t hi, uint64_t lo) "invalid context-cache desc hi 0x%"PRIx64" lo 0x%"PRIx64
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vtd_inv_desc_iotlb_global(void) "iotlb invalidate global"
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vtd_inv_desc_iotlb_domain(uint16_t domain) "iotlb invalidate whole domain 0x%"PRIx16
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vtd_inv_desc_iotlb_pages(uint16_t domain, uint64_t addr, uint8_t mask) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8
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vtd_inv_desc_iotlb_invalid(uint64_t hi, uint64_t lo) "invalid iotlb desc hi 0x%"PRIx64" lo 0x%"PRIx64
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vtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status write addr 0x%"PRIx64" data 0x%"PRIx32
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vtd_inv_desc_wait_irq(const char *msg) "%s"
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vtd_inv_desc_wait_invalid(uint64_t hi, uint64_t lo) "invalid wait desc hi 0x%"PRIx64" lo 0x%"PRIx64
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vtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64
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# hw/i386/amd_iommu.c
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amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" + offset 0x%"PRIx32
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amdvi_cache_update(uint16_t domid, uint8_t bus, uint8_t slot, uint8_t func, uint64_t gpa, uint64_t txaddr) " update iotlb domid 0x%"PRIx16" devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64
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