From bd1ad92ccfa48c44f001ebea17633ef61ff62642 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Thu, 21 Mar 2024 19:42:27 +0100 Subject: [PATCH] target/hppa: Fix ADD/SUB trap on overflow for narrow mode Fixes: c53e401ed9ff ("target/hppa: Remove TARGET_REGISTER_BITS") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Message-Id: <20240321184228.611897-2-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2cb91956da..ceb739c54a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1126,6 +1126,9 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_add_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } /* ??? Need to include overflow from shift. */ gen_helper_tsv(tcg_env, sv); } @@ -1217,6 +1220,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { + if (!d) { + tcg_gen_ext32s_i64(sv, sv); + } gen_helper_tsv(tcg_env, sv); } }