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target/mips: Clean up handling of CP0 register 19 

Clean up handling of CP0 register 19.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-21-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-29 12:03:36 +02:00
parent e8dcfe825a
commit be274dc18e
2 changed files with 36 additions and 32 deletions
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4
target/mips/cpu.h
View File

@ -395,6 +395,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG19__WATCHHI1 1 #define CP0_REG19__WATCHHI1 1
#define CP0_REG19__WATCHHI2 2 #define CP0_REG19__WATCHHI2 2
#define CP0_REG19__WATCHHI3 3 #define CP0_REG19__WATCHHI3 3
#define CP0_REG19__WATCHHI4 4
#define CP0_REG19__WATCHHI5 5
#define CP0_REG19__WATCHHI6 6
#define CP0_REG19__WATCHHI7 7
/* CP0 Register 20 */ /* CP0 Register 20 */
#define CP0_REG20__XCONTEXT 0 #define CP0_REG20__XCONTEXT 0
/* CP0 Register 21 */ /* CP0 Register 21 */

64
target/mips/translate.c
View File

@ -7323,14 +7323,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_19: case CP0_REGISTER_19:
switch (sel) { switch (sel) {
case 0: case CP0_REG19__WATCHHI0:
case 1: case CP0_REG19__WATCHHI1:
case 2: case CP0_REG19__WATCHHI2:
case 3: case CP0_REG19__WATCHHI3:
case 4: case CP0_REG19__WATCHHI4:
case 5: case CP0_REG19__WATCHHI5:
case 6: case CP0_REG19__WATCHHI6:
case 7: case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel); gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi"; register_name = "WatchHi";
@ -8058,14 +8058,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_19: case CP0_REGISTER_19:
switch (sel) { switch (sel) {
case 0: case CP0_REG19__WATCHHI0:
case 1: case CP0_REG19__WATCHHI1:
case 2: case CP0_REG19__WATCHHI2:
case 3: case CP0_REG19__WATCHHI3:
case 4: case CP0_REG19__WATCHHI4:
case 5: case CP0_REG19__WATCHHI5:
case 6: case CP0_REG19__WATCHHI6:
case 7: case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel); gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi"; register_name = "WatchHi";
@ -8795,14 +8795,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_19: case CP0_REGISTER_19:
switch (sel) { switch (sel) {
case 0: case CP0_REG19__WATCHHI0:
case 1: case CP0_REG19__WATCHHI1:
case 2: case CP0_REG19__WATCHHI2:
case 3: case CP0_REG19__WATCHHI3:
case 4: case CP0_REG19__WATCHHI4:
case 5: case CP0_REG19__WATCHHI5:
case 6: case CP0_REG19__WATCHHI6:
case 7: case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel); gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi"; register_name = "WatchHi";
@ -9512,14 +9512,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_19: case CP0_REGISTER_19:
switch (sel) { switch (sel) {
case 0: case CP0_REG19__WATCHHI0:
case 1: case CP0_REG19__WATCHHI1:
case 2: case CP0_REG19__WATCHHI2:
case 3: case CP0_REG19__WATCHHI3:
case 4: case CP0_REG19__WATCHHI4:
case 5: case CP0_REG19__WATCHHI5:
case 6: case CP0_REG19__WATCHHI6:
case 7: case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel); gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi"; register_name = "WatchHi";