tests/tcg/xtensa: enable system tests

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
This commit is contained in:
Alex Bennée 2018-12-06 17:12:44 +00:00
parent c72d9df181
commit be5cac175a
2 changed files with 42 additions and 102 deletions

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@ -1,102 +0,0 @@
-include ../../../config-host.mak
CORE=dc232b
CROSS=xtensa-$(CORE)-elf-
ifndef XT
SIM = ../../../xtensa-softmmu/qemu-system-xtensa
SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel
SIMDEBUG = -s -S
else
SIM = xt-run
SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS)
SIMDEBUG = --gdbserve=0
endif
HOST_CC = gcc
CC = $(CROSS)gcc
AS = $(CROSS)gcc -x assembler-with-cpp
LD = $(CROSS)ld
ASFLAGS = -Wa,--no-absolute-literals
vectors_ASFLAGS = -mtext-section-literals
XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa
INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target/xtensa/core-$(CORE)
XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
LDFLAGS = -Tlinker.ld
CRT = crt.o vectors.o
TESTCASES += test_b.tst
TESTCASES += test_bi.tst
TESTCASES += test_boolean.tst
TESTCASES += test_break.tst
TESTCASES += test_bz.tst
TESTCASES += test_cache.tst
TESTCASES += test_clamps.tst
TESTCASES += test_extui.tst
TESTCASES += test_fail.tst
TESTCASES += test_flix.tst
TESTCASES += test_fp0_arith.tst
TESTCASES += test_fp0_conv.tst
TESTCASES += test_fp1.tst
TESTCASES += test_fp_cpenable.tst
TESTCASES += test_interrupt.tst
TESTCASES += test_loop.tst
TESTCASES += test_lsc.tst
TESTCASES += test_mac16.tst
TESTCASES += test_max.tst
TESTCASES += test_min.tst
TESTCASES += test_mmu.tst
TESTCASES += test_mul16.tst
TESTCASES += test_mul32.tst
TESTCASES += test_nsa.tst
TESTCASES += test_phys_mem.tst
ifdef XT
TESTCASES += test_pipeline.tst
endif
TESTCASES += test_quo.tst
TESTCASES += test_rem.tst
TESTCASES += test_rst0.tst
TESTCASES += test_s32c1i.tst
TESTCASES += test_sar.tst
TESTCASES += test_sext.tst
TESTCASES += test_shift.tst
TESTCASES += test_sr.tst
TESTCASES += test_timer.tst
TESTCASES += test_windowed.tst
all: build
linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S
$(HOST_CC) $(XTENSA_INC) -E -P $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.c
$(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@
%.o: $(XTENSA_SRC_PATH)/%.S
$(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) -c $< -o $@
%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
build: $(TESTCASES)
check: $(addprefix run-, $(TESTCASES))
run-%.tst: %.tst
$(SIM) $(SIMFLAGS) ./$<
run-test_fail.tst: test_fail.tst
! $(SIM) $(SIMFLAGS) ./$<
debug-%.tst: %.tst
$(SIM) $(SIMDEBUG) $(SIMFLAGS) ./$<
host-debug-%.tst: %.tst
gdb --args $(SIM) $(SIMFLAGS) ./$<
clean:
$(RM) -fr $(TESTCASES) $(CRT) linker.ld

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@ -0,0 +1,42 @@
#
# Xtensa softmmu tests
#
ifneq ($(TARGET_WORDS_BIGENDIAN),y)
XTENSA_SRC = $(SRC_PATH)/tests/tcg/xtensa
XTENSA_ALL = $(filter-out $(XTENSA_SRC)/linker.ld.S,$(wildcard $(XTENSA_SRC)/*.S))
XTENSA_TESTS = $(patsubst $(XTENSA_SRC)/%.S, %, $(XTENSA_ALL))
# Filter out common blobs and broken tests
XTENSA_BROKEN_TESTS = crt vectors test_boolean test_pipeline test_fail
XTENSA_USABLE_TESTS = $(filter-out $(XTENSA_BROKEN_TESTS), $(XTENSA_TESTS))
# add to the list of tests
TESTS += $(XTENSA_USABLE_TESTS)
VPATH += $(XTENSA_SRC)
CORE=dc232b
QEMU_OPTS+=-M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel
INCLUDE_DIRS = $(SRC_PATH)/target/xtensa/core-$(CORE)
XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS))
vectors_ASFLAGS = -mtext-section-literals
ASFLAGS = -Wa,--no-absolute-literals
LDFLAGS = -Tlinker.ld -nostartfiles -nostdlib
CRT = crt.o vectors.o
linker.ld: linker.ld.S
$(CC) $(XTENSA_INC) -E -P $< -o $@
$(XTENSA_USABLE_TESTS): linker.ld macros.inc $(CRT) Makefile.softmmu-target
# special rule for common blobs
%.o: %.S
$(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) -c $< -o $@
%: %.S
$(CC) $(XTENSA_INC) $(ASFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT)
endif