memory: move endianness compensation to memory core
Instead of doing device endianness compensation in cpu_register_io_memory(), do it in the memory core. Signed-off-by: Avi Kivity <avi@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Avi Kivity
parent
7638e0d220
commit
be675c9720
@ -33,7 +33,7 @@ void qemu_ram_free_from_ptr(ram_addr_t addr);
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int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
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CPUWriteMemoryFunc * const *mem_write,
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void *opaque, enum device_endian endian);
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void *opaque);
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void cpu_unregister_io_memory(int table_address);
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void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
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142
exec.c
142
exec.c
@ -3507,8 +3507,7 @@ static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
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mmio = g_malloc0(sizeof(subpage_t));
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mmio->base = base;
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subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio,
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DEVICE_NATIVE_ENDIAN);
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subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
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#if defined(DEBUG_SUBPAGE)
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printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
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mmio, base, TARGET_PAGE_SIZE, subpage_memory);
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@ -3532,106 +3531,6 @@ static int get_free_io_mem_idx(void)
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return -1;
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}
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/*
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* Usually, devices operate in little endian mode. There are devices out
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* there that operate in big endian too. Each device gets byte swapped
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* mmio if plugged onto a CPU that does the other endianness.
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*
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* CPU Device swap?
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*
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* little little no
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* little big yes
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* big little yes
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* big big no
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*/
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typedef struct SwapEndianContainer {
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CPUReadMemoryFunc *read[3];
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CPUWriteMemoryFunc *write[3];
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void *opaque;
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} SwapEndianContainer;
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static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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SwapEndianContainer *c = opaque;
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val = c->read[0](c->opaque, addr);
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return val;
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}
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static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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SwapEndianContainer *c = opaque;
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val = bswap16(c->read[1](c->opaque, addr));
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return val;
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}
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static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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SwapEndianContainer *c = opaque;
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val = bswap32(c->read[2](c->opaque, addr));
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return val;
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}
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static CPUReadMemoryFunc * const swapendian_readfn[3]={
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swapendian_mem_readb,
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swapendian_mem_readw,
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swapendian_mem_readl
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};
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static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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SwapEndianContainer *c = opaque;
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c->write[0](c->opaque, addr, val);
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}
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static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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SwapEndianContainer *c = opaque;
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c->write[1](c->opaque, addr, bswap16(val));
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}
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static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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SwapEndianContainer *c = opaque;
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c->write[2](c->opaque, addr, bswap32(val));
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}
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static CPUWriteMemoryFunc * const swapendian_writefn[3]={
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swapendian_mem_writeb,
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swapendian_mem_writew,
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swapendian_mem_writel
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};
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static void swapendian_init(int io_index)
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{
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SwapEndianContainer *c = g_malloc(sizeof(SwapEndianContainer));
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int i;
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/* Swap mmio for big endian targets */
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c->opaque = io_mem_opaque[io_index];
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for (i = 0; i < 3; i++) {
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c->read[i] = io_mem_read[io_index][i];
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c->write[i] = io_mem_write[io_index][i];
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io_mem_read[io_index][i] = swapendian_readfn[i];
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io_mem_write[io_index][i] = swapendian_writefn[i];
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}
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io_mem_opaque[io_index] = c;
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}
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static void swapendian_del(int io_index)
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{
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if (io_mem_read[io_index][0] == swapendian_readfn[0]) {
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g_free(io_mem_opaque[io_index]);
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}
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}
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/* mem_read and mem_write are arrays of functions containing the
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function to access byte (index 0), word (index 1) and dword (index
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2). Functions can be omitted with a NULL function pointer.
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@ -3642,7 +3541,7 @@ static void swapendian_del(int io_index)
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static int cpu_register_io_memory_fixed(int io_index,
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CPUReadMemoryFunc * const *mem_read,
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CPUWriteMemoryFunc * const *mem_write,
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void *opaque, enum device_endian endian)
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void *opaque)
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{
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int i;
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@ -3666,30 +3565,14 @@ static int cpu_register_io_memory_fixed(int io_index,
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}
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io_mem_opaque[io_index] = opaque;
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switch (endian) {
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case DEVICE_BIG_ENDIAN:
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#ifndef TARGET_WORDS_BIGENDIAN
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swapendian_init(io_index);
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#endif
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break;
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case DEVICE_LITTLE_ENDIAN:
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#ifdef TARGET_WORDS_BIGENDIAN
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swapendian_init(io_index);
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#endif
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break;
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case DEVICE_NATIVE_ENDIAN:
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default:
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break;
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}
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return (io_index << IO_MEM_SHIFT);
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}
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int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
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CPUWriteMemoryFunc * const *mem_write,
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void *opaque, enum device_endian endian)
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void *opaque)
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{
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return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian);
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return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
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}
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void cpu_unregister_io_memory(int io_table_address)
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@ -3697,8 +3580,6 @@ void cpu_unregister_io_memory(int io_table_address)
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int i;
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int io_index = io_table_address >> IO_MEM_SHIFT;
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swapendian_del(io_index);
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for (i=0;i < 3; i++) {
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io_mem_read[io_index][i] = unassigned_mem_read[i];
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io_mem_write[io_index][i] = unassigned_mem_write[i];
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@ -3712,23 +3593,18 @@ static void io_mem_init(void)
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int i;
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cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read,
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unassigned_mem_write, NULL,
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DEVICE_NATIVE_ENDIAN);
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unassigned_mem_write, NULL);
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cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read,
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unassigned_mem_write, NULL,
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DEVICE_NATIVE_ENDIAN);
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unassigned_mem_write, NULL);
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cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read,
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notdirty_mem_write, NULL,
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DEVICE_NATIVE_ENDIAN);
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notdirty_mem_write, NULL);
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cpu_register_io_memory_fixed(IO_MEM_SUBPAGE_RAM, subpage_ram_read,
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subpage_ram_write, NULL,
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DEVICE_NATIVE_ENDIAN);
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subpage_ram_write, NULL);
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for (i=0; i<5; i++)
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io_mem_used[i] = 1;
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io_mem_watch = cpu_register_io_memory(watch_mem_read,
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watch_mem_write, NULL,
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DEVICE_NATIVE_ENDIAN);
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watch_mem_write, NULL);
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}
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static void memory_map_init(void)
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37
memory.c
37
memory.c
@ -857,6 +857,15 @@ static void memory_region_destructor_rom_device(MemoryRegion *mr)
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cpu_unregister_io_memory(mr->ram_addr & ~(TARGET_PAGE_MASK | IO_MEM_ROMD));
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}
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static bool memory_region_wrong_endianness(MemoryRegion *mr)
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{
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#ifdef TARGET_BIG_ENDIAN
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return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
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#else
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return mr->ops->endianness == DEVICE_BIG_ENDIAN;
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#endif
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}
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void memory_region_init(MemoryRegion *mr,
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const char *name,
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uint64_t size)
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@ -967,12 +976,24 @@ static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr)
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static uint32_t memory_region_read_thunk_w(void *mr, target_phys_addr_t addr)
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{
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return memory_region_read_thunk_n(mr, addr, 2);
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uint32_t data;
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data = memory_region_read_thunk_n(mr, addr, 2);
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if (memory_region_wrong_endianness(mr)) {
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data = bswap16(data);
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}
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return data;
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}
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static uint32_t memory_region_read_thunk_l(void *mr, target_phys_addr_t addr)
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{
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return memory_region_read_thunk_n(mr, addr, 4);
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uint32_t data;
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data = memory_region_read_thunk_n(mr, addr, 4);
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if (memory_region_wrong_endianness(mr)) {
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data = bswap32(data);
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}
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return data;
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}
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static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr,
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@ -984,12 +1005,18 @@ static void memory_region_write_thunk_b(void *mr, target_phys_addr_t addr,
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static void memory_region_write_thunk_w(void *mr, target_phys_addr_t addr,
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uint32_t data)
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{
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if (memory_region_wrong_endianness(mr)) {
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data = bswap16(data);
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}
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memory_region_write_thunk_n(mr, addr, 2, data);
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}
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static void memory_region_write_thunk_l(void *mr, target_phys_addr_t addr,
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uint32_t data)
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{
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if (memory_region_wrong_endianness(mr)) {
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data = bswap32(data);
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}
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memory_region_write_thunk_n(mr, addr, 4, data);
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}
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@ -1014,8 +1041,7 @@ static void memory_region_prepare_ram_addr(MemoryRegion *mr)
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mr->destructor = memory_region_destructor_iomem;
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mr->ram_addr = cpu_register_io_memory(memory_region_read_thunk,
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memory_region_write_thunk,
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mr,
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mr->ops->endianness);
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mr);
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mr->backend_registered = true;
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}
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@ -1082,8 +1108,7 @@ void memory_region_init_rom_device(MemoryRegion *mr,
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mr->ram_addr = qemu_ram_alloc(size, mr);
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mr->ram_addr |= cpu_register_io_memory(memory_region_read_thunk,
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memory_region_write_thunk,
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mr,
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mr->ops->endianness);
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mr);
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mr->ram_addr |= IO_MEM_ROMD;
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mr->backend_registered = true;
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}
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