OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

hw/omap_dma, hw/omap_spi: Explicitly mark fallthroughs 

Explicitly mark the fallthroughs as intentional in the code
pattern where we gradually increment an index before falling
into the code to read/write that array entry:
  case THINGY_3: idx++;
  case THINGY_2: idx++;
  case THINGY_1: idx++;
  case THINGY_0: return s->thingy[idx];

This makes static analysers happy.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Peter Maydell 2013-01-21 12:50:53 +00:00 committed by Blue Swirl
parent 139bd956ea
commit be688dfb8d
2 changed files with 36 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
hw/omap_dma.c
View File

@ -1709,19 +1709,25 @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
/* fall through */
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
/* fall through */
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
/* fall through */
case 0x08: /* DMA4_IRQSTATUS_L0 */
return s->irqstat[irqn];
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
/* fall through */
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
/* fall through */
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
/* fall through */
case 0x18: /* DMA4_IRQENABLE_L0 */
return s->irqen[irqn];
@ -1856,10 +1862,13 @@ static void omap_dma4_write(void *opaque, hwaddr addr,
switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
/* fall through */
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
/* fall through */
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
/* fall through */
case 0x08: /* DMA4_IRQSTATUS_L0 */
s->irqstat[irqn] &= ~value;
if (!s->irqstat[irqn])
@ -1868,10 +1877,13 @@ static void omap_dma4_write(void *opaque, hwaddr addr,
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
/* fall through */
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
/* fall through */
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
/* fall through */
case 0x18: /* DMA4_IRQENABLE_L0 */
s->irqen[irqn] = value;
return;

24
hw/omap_spi.c
View File

@ -167,32 +167,47 @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
return s->control;
case 0x68: ch ++;
/* fall through */
case 0x54: ch ++;
/* fall through */
case 0x40: ch ++;
/* fall through */
case 0x2c: /* MCSPI_CHCONF */
return s->ch[ch].config;
case 0x6c: ch ++;
/* fall through */
case 0x58: ch ++;
/* fall through */
case 0x44: ch ++;
/* fall through */
case 0x30: /* MCSPI_CHSTAT */
return s->ch[ch].status;
case 0x70: ch ++;
/* fall through */
case 0x5c: ch ++;
/* fall through */
case 0x48: ch ++;
/* fall through */
case 0x34: /* MCSPI_CHCTRL */
return s->ch[ch].control;
case 0x74: ch ++;
/* fall through */
case 0x60: ch ++;
/* fall through */
case 0x4c: ch ++;
/* fall through */
case 0x38: /* MCSPI_TX */
return s->ch[ch].tx;
case 0x78: ch ++;
/* fall through */
case 0x64: ch ++;
/* fall through */
case 0x50: ch ++;
/* fall through */
case 0x3c: /* MCSPI_RX */
s->ch[ch].status &= ~(1 << 0); /* RXS */
ret = s->ch[ch].rx;
@ -269,8 +284,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr,
break;
case 0x68: ch ++;
/* fall through */
case 0x54: ch ++;
/* fall through */
case 0x40: ch ++;
/* fall through */
case 0x2c: /* MCSPI_CHCONF */
if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
omap_mcspi_dmarequest_update(s->ch + ch);
@ -283,8 +301,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr,
break;
case 0x70: ch ++;
/* fall through */
case 0x5c: ch ++;
/* fall through */
case 0x48: ch ++;
/* fall through */
case 0x34: /* MCSPI_CHCTRL */
if (value & ~s->ch[ch].control & 1) { /* EN */
s->ch[ch].control |= 1;
@ -294,8 +315,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr,
break;
case 0x74: ch ++;
/* fall through */
case 0x60: ch ++;
/* fall through */
case 0x4c: ch ++;
/* fall through */
case 0x38: /* MCSPI_TX */
s->ch[ch].tx = value;
s->ch[ch].status &= ~(1 << 1); /* TXS */