From be8b49de2491145a7aad3201803327b6f568cbd3 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 1 Mar 2018 13:08:26 +0100 Subject: [PATCH] s390x/tcg: fix loading 31bit PSWs with the highest bit set Let's also put the 31-bit hack in front of the REAL MMU, otherwise right now we get errors when loading a PSW where the highest bit is set (e.g. via s390-netboot.img). The highest bit is not masked away, therefore we inject addressing exceptions into the guest. The proper fix will later be to do all address wrapping before accessing the MMU - so we won't get any "wrong" entries in there (which makes flushing also easier). But that will require more work (wrapping in load_psw, wrapping when incrementing the PC, wrapping every memory access). This fixes the tests/pxe-test test. Signed-off-by: David Hildenbrand Message-Id: <20180301120826.6847-1-david@redhat.com> Signed-off-by: Cornelia Huck --- target/s390x/excp_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 411051edc3..dfee221111 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -107,6 +107,10 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, return 1; } } else if (mmu_idx == MMU_REAL_IDX) { + /* 31-Bit mode */ + if (!(env->psw.mask & PSW_MASK_64)) { + vaddr &= 0x7fffffff; + } if (mmu_translate_real(env, vaddr, rw, &raddr, &prot)) { return 1; }