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target-mips: correct the values in the DSP tests

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Five tests files for DSP instructions had wrong expected values in the tests.
This change fixes this, and this has been cross-checked by running the same
test binaries on Malta 74K board.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Petar Jovanovic 2013-07-29 12:49:05 +02:00 committed by Aurelien Jarno
parent dbe49aea76
commit beb3faaa00
5 changed files with 37 additions and 33 deletions
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10
tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c
View File

@ -9,8 +9,8 @@ int main()
rs = 0xBC0123AD;
rt = 0x01643721;
resulth = 0x04;
resultl = 0xEE9794A3;
resulth = 0x00000004;
resultl = 0xF15F94A3;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"
@ -23,12 +23,12 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
ach = 0x1424Ef1f;
ach = 0x1424EF1F;
acl = 0x1035219A;
rs = 0x800083AD;
rt = 0x80003721;
resulth = 0x1424ef1e;
resultl = 0x577ed901;
resulth = 0x1424EF1E;
resultl = 0xC5C0D901;
__asm
("mthi %0, $ac1\n\t"
"mtlo %1, $ac1\n\t"

16
tests/tcg/mips/mips32-dsp/maq_s_w_phl.c
View File

@ -10,12 +10,12 @@ int main()
int resulth, resultl;
int resdsp;
achi = 0x05;
acli = 0xB4CB;
achi = 0x00000005;
acli = 0x0000B4CB;
rs = 0xFF060000;
rt = 0xCB000000;
resulth = 0x04;
resultl = 0x947438CB;
resulth = 0x00000005;
resultl = 0x006838CB;
__asm
("mthi %2, $ac1\n\t"
@ -29,12 +29,12 @@ int main()
assert(resulth == acho);
assert(resultl == aclo);
achi = 0x06;
acli = 0xB4CB;
achi = 0x00000006;
acli = 0x0000B4CB;
rs = 0x80000000;
rt = 0x80000000;
resulth = 0x6;
resultl = 0x8000b4ca;
resulth = 0x00000006;
resultl = 0x8000B4CA;
resdsp = 1;
__asm

24
tests/tcg/mips/mips32-dsp/maq_s_w_phr.c
View File

@ -10,12 +10,12 @@ int main()
int resulth, resultl;
int resdsp;
achi = 0x05;
acli = 0xB4CB;
rs = 0xFF06;
rt = 0xCB00;
resulth = 0x04;
resultl = 0x947438CB;
achi = 0x00000005;
acli = 0x0000B4CB;
rs = 0x0000FF06;
rt = 0x0000CB00;
resulth = 0x00000005;
resultl = 0x006838CB;
__asm
("mthi %2, $ac1\n\t"
@ -29,12 +29,12 @@ int main()
assert(resulth == acho);
assert(resultl == aclo);
achi = 0x06;
acli = 0xB4CB;
rs = 0x8000;
rt = 0x8000;
resulth = 0x6;
resultl = 0x8000b4ca;
achi = 0x00000006;
acli = 0x0000B4CB;
rs = 0x00008000;
rt = 0x00008000;
resulth = 0x00000006;
resultl = 0x8000B4CA;
resdsp = 1;
__asm

12
tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c
View File

@ -4,14 +4,17 @@
int main()
{
int rs, rt, dsp;
int ach = 5, acl = 5;
int ach, acl;
int resulth, resultl, resultdsp;
ach = 0x00000005;
acl = 0x00000005;
rs = 0x00FF00FF;
rt = 0x00010002;
resulth = 0x00;
resultl = 0x7FFFFFFF;
resultdsp = 0x01;
dsp = 0;
__asm
("wrdsp %2\n\t"
"mthi %0, $ac1\n\t"
@ -27,13 +30,14 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
ach = 9;
acl = 0xb;
ach = 0x00000009;
acl = 0x0000000B;
rs = 0x800000FF;
rt = 0x00018000;
resulth = 0x00;
resultl = 0x7fffffff;
resultl = 0x7FFFFFFF;
resultdsp = 0x01;
dsp = 0;
__asm
("wrdsp %2\n\t"
"mthi %0, $ac1\n\t"

8
tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c
View File

@ -9,8 +9,8 @@ int main()
rs = 0xBC0123AD;
rt = 0x01643721;
resulth = 0x04;
resultl = 0xAEA3E09B;
resulth = 0x00000005;
resultl = 0x1CE5E09B;
resultdsp = 0x00;
__asm
("mthi %0, $ac1\n\t"
@ -27,12 +27,12 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
ach = 0x99f13005;
ach = 0x99F13005;
acl = 0x51730062;
rs = 0x80008000;
rt = 0x80008000;
resulth = 0x99f13004;
resulth = 0x99F13004;
resultl = 0x51730064;
resultdsp = 0x01;
__asm