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Mention missing CPU save/restore.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4381 c046a42c-6fe2-441c-8c8c-71466251a162
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ths 2008-05-07 15:39:12 +00:00
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commit bec19c0932
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target-mips/TODO
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@ -29,6 +29,7 @@ General
To cope with these differences, Qemu currently flushes the TLB at
each ASID change. Using the MMU modes to implement ASIDs hinges on
implementing the global bit efficiently.
- save/restore of the CPU state is not implemented (see machine.c).
MIPS64
------