OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target-mips: Provide function to test if a CPU supports an ISA

Browse Source 
Provide a new cpu_supports_isa function which allows callers to
determine whether a CPU supports one of the ISA_ flags, by testing
whether the associated struct mips_def_t sets the ISA flags in its
insn_flags field.

An example use of this is to allow boards which generate bootloader code
to determine the properties of the CPU that will be used, for example
whether the CPU is 64 bit or which architecture revision it implements.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
This commit is contained in:
Paul Burton 2016-09-08 15:51:54 +01:00 committed by Yongbok Kim
parent 2e2a1b4648
commit bed9e5ceb1
2 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/mips/cpu.h
View File

@ -815,6 +815,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
bool cpu_supports_cps_smp(const char *cpu_model); bool cpu_supports_cps_smp(const char *cpu_model);
bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
void cpu_set_exception_base(int vp_index, target_ulong address); void cpu_set_exception_base(int vp_index, target_ulong address);
/* TODO QOM'ify CPU reset and remove */ /* TODO QOM'ify CPU reset and remove */

10
target/mips/translate.c
View File

@ -20233,6 +20233,16 @@ bool cpu_supports_cps_smp(const char *cpu_model)
return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
} }
bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
{
const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
if (!def) {
return false;
}
return (def->insn_flags & isa) != 0;
}
void cpu_set_exception_base(int vp_index, target_ulong address) void cpu_set_exception_base(int vp_index, target_ulong address)
{ {
MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));