hw/char/sh_serial: QOM-ify
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <92902ba34fdf2c8c62232365fbb6531b1036d557.1635541329.git.balaton@eik.bme.hu> [PMD: Use g_strdup() to initialize DeviceState::id] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan
Philippe Mathieu-Daudé
parent
017f77bbf7
commit
beeb520925
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@ -26,7 +26,11 @@
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/sh4/sh.h"
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#include "chardev/char-fe.h"
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#include "qapi/error.h"
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@ -42,10 +46,10 @@
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#define SH_RX_FIFO_LENGTH (16)
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typedef struct {
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MemoryRegion iomem;
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MemoryRegion iomem_p4;
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MemoryRegion iomem_a7;
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OBJECT_DECLARE_SIMPLE_TYPE(SHSerialState, SH_SERIAL)
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struct SHSerialState {
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SysBusDevice parent;
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uint8_t smr;
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uint8_t brr;
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uint8_t scr;
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@ -59,8 +63,7 @@ typedef struct {
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uint8_t rx_tail;
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uint8_t rx_head;
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int freq;
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int feat;
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uint8_t feat;
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int flags;
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int rtrg;
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@ -73,7 +76,11 @@ typedef struct {
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qemu_irq txi;
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qemu_irq tei;
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qemu_irq bri;
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} SHSerialState;
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};
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typedef struct {} SHSerialStateClass;
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OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE)
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static void sh_serial_clear_fifo(SHSerialState *s)
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{
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@ -381,8 +388,10 @@ static const MemoryRegionOps sh_serial_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void sh_serial_reset(SHSerialState *s)
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static void sh_serial_reset(DeviceState *dev)
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{
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SHSerialState *s = SH_SERIAL(dev);
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s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
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s->rtrg = 1;
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@ -400,33 +409,21 @@ static void sh_serial_reset(SHSerialState *s)
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sh_serial_clear_fifo(s);
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}
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void sh_serial_init(MemoryRegion *sysmem,
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hwaddr base, int feat,
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uint32_t freq, Chardev *chr,
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qemu_irq eri_source,
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qemu_irq rxi_source,
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qemu_irq txi_source,
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qemu_irq tei_source,
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qemu_irq bri_source)
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static void sh_serial_realize(DeviceState *d, Error **errp)
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{
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SHSerialState *s = g_malloc0(sizeof(*s));
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SHSerialState *s = SH_SERIAL(d);
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MemoryRegion *iomem = g_malloc(sizeof(*iomem));
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s->feat = feat;
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sh_serial_reset(s);
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assert(d->id);
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memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28);
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sysbus_init_mmio(SYS_BUS_DEVICE(d), iomem);
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qdev_init_gpio_out_named(d, &s->eri, "eri", 1);
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qdev_init_gpio_out_named(d, &s->rxi, "rxi", 1);
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qdev_init_gpio_out_named(d, &s->txi, "txi", 1);
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qdev_init_gpio_out_named(d, &s->tei, "tei", 1);
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qdev_init_gpio_out_named(d, &s->bri, "bri", 1);
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memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
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"serial", 0x100000000ULL);
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memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
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0, 0x28);
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memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
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memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
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0, 0x28);
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memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
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if (chr) {
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qemu_chr_fe_init(&s->chr, chr, &error_abort);
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if (qemu_chr_fe_backend_connected(&s->chr)) {
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qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
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sh_serial_receive1,
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sh_serial_event, NULL, s, NULL, true);
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@ -435,9 +432,32 @@ void sh_serial_init(MemoryRegion *sysmem,
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timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL,
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sh_serial_timeout_int, s);
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s->etu = NANOSECONDS_PER_SECOND / 9600;
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s->eri = eri_source;
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s->rxi = rxi_source;
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s->txi = txi_source;
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s->tei = tei_source;
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s->bri = bri_source;
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}
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static void sh_serial_finalize(Object *obj)
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{
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SHSerialState *s = SH_SERIAL(obj);
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timer_del(&s->fifo_timeout_timer);
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}
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static void sh_serial_init(Object *obj)
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{
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}
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static Property sh_serial_properties[] = {
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DEFINE_PROP_CHR("chardev", SHSerialState, chr),
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DEFINE_PROP_UINT8("features", SHSerialState, feat, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void sh_serial_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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device_class_set_props(dc, sh_serial_properties);
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dc->realize = sh_serial_realize;
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dc->reset = sh_serial_reset;
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/* Reason: part of SuperH CPU/SoC, needs to be wired up */
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dc->user_creatable = false;
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}
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@ -24,9 +24,13 @@
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/sh4/sh.h"
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#include "sysemu/sysemu.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "sh7750_regs.h"
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#include "sh7750_regnames.h"
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#include "hw/sh4/sh_intc.h"
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@ -762,6 +766,9 @@ static const MemoryRegionOps sh7750_mmct_ops = {
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SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
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{
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SH7750State *s;
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DeviceState *dev;
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SysBusDevice *sb;
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MemoryRegion *mr, *alias;
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s = g_malloc0(sizeof(SH7750State));
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s->cpu = cpu;
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@ -807,21 +814,40 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
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cpu->env.intc_handle = &s->intc;
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sh_serial_init(sysmem, 0x1fe00000,
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0, s->periph_freq, serial_hd(0),
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s->intc.irqs[SCI1_ERI],
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s->intc.irqs[SCI1_RXI],
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s->intc.irqs[SCI1_TXI],
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s->intc.irqs[SCI1_TEI],
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NULL);
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sh_serial_init(sysmem, 0x1fe80000,
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SH_SERIAL_FEAT_SCIF,
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s->periph_freq, serial_hd(1),
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s->intc.irqs[SCIF_ERI],
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s->intc.irqs[SCIF_RXI],
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s->intc.irqs[SCIF_TXI],
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NULL,
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s->intc.irqs[SCIF_BRI]);
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/* SCI */
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dev = qdev_new(TYPE_SH_SERIAL);
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dev->id = g_strdup("sci");
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qdev_prop_set_chr(dev, "chardev", serial_hd(0));
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sb = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sb, &error_fatal);
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sysbus_mmio_map(sb, 0, 0xffe00000);
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alias = g_malloc(sizeof(*alias));
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mr = sysbus_mmio_get_region(sb, 0);
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memory_region_init_alias(alias, OBJECT(dev), "sci-a7", mr,
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0, memory_region_size(mr));
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memory_region_add_subregion(sysmem, A7ADDR(0xffe00000), alias);
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qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]);
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qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]);
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qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]);
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qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]);
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/* SCIF */
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dev = qdev_new(TYPE_SH_SERIAL);
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dev->id = g_strdup("scif");
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qdev_prop_set_chr(dev, "chardev", serial_hd(1));
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qdev_prop_set_uint8(dev, "features", SH_SERIAL_FEAT_SCIF);
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sb = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sb, &error_fatal);
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sysbus_mmio_map(sb, 0, 0xffe80000);
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alias = g_malloc(sizeof(*alias));
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mr = sysbus_mmio_get_region(sb, 0);
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memory_region_init_alias(alias, OBJECT(dev), "scif-a7", mr,
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0, memory_region_size(mr));
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memory_region_add_subregion(sysmem, A7ADDR(0xffe80000), alias);
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qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]);
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qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]);
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qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCIF_TXI]);
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qdev_connect_gpio_out_named(dev, "bri", 0, s->intc.irqs[SCIF_BRI]);
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tmu012_init(sysmem, 0x1fd80000,
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TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
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@ -54,15 +54,8 @@ int sh7750_register_io_device(struct SH7750State *s,
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sh7750_io_device *device);
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/* sh_serial.c */
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#define TYPE_SH_SERIAL "sh-serial"
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#define SH_SERIAL_FEAT_SCIF (1 << 0)
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void sh_serial_init(MemoryRegion *sysmem,
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hwaddr base, int feat,
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uint32_t freq, Chardev *chr,
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qemu_irq eri_source,
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qemu_irq rxi_source,
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qemu_irq txi_source,
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qemu_irq tei_source,
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qemu_irq bri_source);
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/* sh7750.c */
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qemu_irq sh7750_irl(struct SH7750State *s);
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