enabled MMX, PAE and SEP
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1284 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -98,7 +98,7 @@ CPUX86State *cpu_x86_init(void)
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#else
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/* pentium pro */
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family = 6;
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model = 1;
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model = 3;
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stepping = 3;
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#endif
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#endif
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@ -106,14 +106,18 @@ CPUX86State *cpu_x86_init(void)
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env->cpuid_features = (CPUID_FP87 | CPUID_DE | CPUID_PSE |
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CPUID_TSC | CPUID_MSR | CPUID_MCE |
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CPUID_CX8 | CPUID_PGE | CPUID_CMOV);
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env->cpuid_ext_features = 0;
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env->cpuid_features |= CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | CPUID_PAE | CPUID_SEP;
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#ifdef TARGET_X86_64
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/* currently not enabled for std i386 because not fully tested */
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env->cpuid_features |= CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2;
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env->cpuid_features |= CPUID_APIC | CPUID_PAE;
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env->cpuid_features |= CPUID_APIC;
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#endif
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}
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cpu_single_env = env;
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cpu_reset(env);
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#ifdef USE_KQEMU
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kqemu_init(env);
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#endif
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return env;
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}
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@ -453,6 +457,8 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
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((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
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}
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/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
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the PDPT */
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void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
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{
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env->cr[3] = new_cr3;
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