From bb2ed009e7e4b278c0234143f6b6c1126f68ba35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:50 +0100 Subject: [PATCH 01/14] isa: add memory space parameter to isa_bus_new MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, keep current behaviour by always using get_system_memory(). Also use QOM casts when possible. Signed-off-by: Hervé Poussineau Reviewed-by: Paolo Bonzini Signed-off-by: Leon Alrae --- hw/alpha/typhoon.c | 2 +- hw/i386/pc_piix.c | 2 +- hw/isa/i82378.c | 3 ++- hw/isa/isa-bus.c | 11 ++++++++--- hw/isa/lpc_ich9.c | 2 +- hw/isa/piix4.c | 3 ++- hw/isa/vt82c686.c | 3 ++- hw/mips/mips_jazz.c | 2 +- hw/mips/mips_r4k.c | 2 +- hw/pci-host/piix.c | 3 ++- hw/sparc64/sun4u.c | 3 ++- include/hw/isa/isa.h | 4 +++- 12 files changed, 26 insertions(+), 14 deletions(-) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 53100061d2..62af946105 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -920,7 +920,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, { qemu_irq isa_pci_irq, *isa_irqs; - *isa_bus = isa_bus_new(NULL, &s->pchip.reg_io); + *isa_bus = isa_bus_new(NULL, get_system_memory(), &s->pchip.reg_io); isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1); isa_irqs = i8259_init(*isa_bus, isa_pci_irq); isa_bus_irqs(*isa_bus, isa_irqs); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 38b42b05f8..de75cf0e87 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -208,7 +208,7 @@ static void pc_init1(MachineState *machine, } else { pci_bus = NULL; i440fx_state = NULL; - isa_bus = isa_bus_new(NULL, system_io); + isa_bus = isa_bus_new(NULL, get_system_memory(), system_io); no_hpet = 1; } isa_bus_irqs(isa_bus, gsi); diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index a7d9aa6da1..0dc440df5c 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -75,7 +75,8 @@ static int i82378_initfn(PCIDevice *pci) pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */ - isabus = isa_bus_new(dev, pci_address_space_io(pci)); + isabus = isa_bus_new(dev, get_system_memory(), + pci_address_space_io(pci)); /* This device has: 2 82C59 (irq) diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c index cc85e538b1..fd6a3a19e7 100644 --- a/hw/isa/isa-bus.c +++ b/hw/isa/isa-bus.c @@ -21,7 +21,6 @@ #include "hw/sysbus.h" #include "sysemu/sysemu.h" #include "hw/isa/isa.h" -#include "exec/address-spaces.h" static ISABus *isabus; hwaddr isa_mem_base = 0; @@ -44,7 +43,8 @@ static const TypeInfo isa_bus_info = { .class_init = isa_bus_class_init, }; -ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io) +ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space, + MemoryRegion *address_space_io) { if (isabus) { fprintf(stderr, "Can't create a second ISA bus\n"); @@ -56,6 +56,7 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io) } isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL)); + isabus->address_space = address_space; isabus->address_space_io = address_space_io; return isabus; } @@ -250,7 +251,11 @@ static char *isabus_get_fw_dev_path(DeviceState *dev) MemoryRegion *isa_address_space(ISADevice *dev) { - return get_system_memory(); + if (dev) { + return isa_bus_from_device(dev)->address_space; + } + + return isabus->address_space; } MemoryRegion *isa_address_space_io(ISADevice *dev) diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 530b074551..231de74414 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -575,7 +575,7 @@ static int ich9_lpc_init(PCIDevice *d) ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); ISABus *isa_bus; - isa_bus = isa_bus_new(&d->qdev, get_system_io()); + isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io()); pci_set_long(d->wmask + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 1aa17d7cf6..0cacc3bd3e 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -86,7 +86,8 @@ static int piix4_initfn(PCIDevice *dev) { PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev); - isa_bus_new(&d->dev.qdev, pci_address_space_io(dev)); + isa_bus_new(DEVICE(d), get_system_memory(), + pci_address_space_io(dev)); piix4_dev = &d->dev; qemu_register_reset(piix4_reset, d); return 0; diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 17510ce528..b223526bde 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -429,7 +429,8 @@ static int vt82c686b_initfn(PCIDevice *d) uint8_t *wmask; int i; - isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d)); + isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), + pci_address_space_io(d)); pci_conf = d->config; pci_config_set_prog_interface(pci_conf, 0x0); diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 3f33093fd9..de35299931 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -219,7 +219,7 @@ static void mips_jazz_init(MemoryRegion *address_space, memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); /* ISA devices */ - isa_bus = isa_bus_new(NULL, address_space_io); + isa_bus = isa_bus_new(NULL, get_system_memory(), address_space_io); i8259 = i8259_init(isa_bus, env->irq[4]); isa_bus_irqs(isa_bus, i8259); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index a7fe0ceadf..5b982f2bde 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -268,7 +268,7 @@ void mips_r4k_init(MachineState *machine) cpu_mips_clock_init(env); /* The PIC is attached to the MIPS CPU INT0 pin */ - isa_bus = isa_bus_new(NULL, get_system_io()); + isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io()); i8259 = i8259_init(isa_bus, env->irq[2]); isa_bus_irqs(isa_bus, i8259); diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 1530038cb0..8ea718e18e 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -635,7 +635,8 @@ static int piix3_initfn(PCIDevice *dev) { PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); - isa_bus_new(DEVICE(d), pci_address_space_io(dev)); + isa_bus_new(DEVICE(d), get_system_memory(), + pci_address_space_io(dev)); memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 3ff5bd8871..4620cc613a 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -596,7 +596,8 @@ pci_ebus_init1(PCIDevice *pci_dev) { EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); - isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev)); + isa_bus_new(DEVICE(pci_dev), get_system_memory(), + pci_address_space_io(pci_dev)); pci_dev->config[0x04] = 0x06; // command = bus master, pci mem pci_dev->config[0x05] = 0x00; diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index e0c749f9e9..c6218224d5 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -36,6 +36,7 @@ struct ISABus { BusState parent_obj; /*< public >*/ + MemoryRegion *address_space; MemoryRegion *address_space_io; qemu_irq *irqs; }; @@ -50,7 +51,8 @@ struct ISADevice { int ioport_id; }; -ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io); +ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space, + MemoryRegion *address_space_io); void isa_bus_irqs(ISABus *bus, qemu_irq *irqs); qemu_irq isa_get_irq(ISADevice *dev, int isairq); void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq); From f33772c8510ffe31b29c4bd9fc949f32f02a3954 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:51 +0100 Subject: [PATCH 02/14] jazz: do not explode QEMUMachineInitArgs structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also remove address_space and address_space_io parameters, which where always get_system_memory() and get_system_io(). Signed-off-by: Hervé Poussineau Signed-off-by: Leon Alrae --- hw/mips/mips_jazz.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index de35299931..738e9c73ec 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -120,12 +120,12 @@ static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); } -static void mips_jazz_init(MemoryRegion *address_space, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - const char *cpu_model, +static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) { + MemoryRegion *address_space = get_system_memory(); + MemoryRegion *address_space_io = get_system_io(); + const char *cpu_model = machine->cpu_model; char *filename; int bios_size, n; MIPSCPU *cpu; @@ -179,7 +179,8 @@ static void mips_jazz_init(MemoryRegion *address_space, cc->do_unassigned_access = mips_jazz_do_unassigned_access; /* allocate RAM */ - memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size, &error_abort); + memory_region_init_ram(ram, NULL, "mips_jazz.ram", machine->ram_size, + &error_abort); vmstate_register_ram_global(ram); memory_region_add_subregion(address_space, 0, ram); @@ -333,19 +334,13 @@ static void mips_jazz_init(MemoryRegion *address_space, static void mips_magnum_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; - mips_jazz_init(get_system_memory(), get_system_io(), - ram_size, cpu_model, JAZZ_MAGNUM); + mips_jazz_init(machine, JAZZ_MAGNUM); } static void mips_pica61_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; - const char *cpu_model = machine->cpu_model; - mips_jazz_init(get_system_memory(), get_system_io(), - ram_size, cpu_model, JAZZ_PICA61); + mips_jazz_init(machine, JAZZ_PICA61); } static QEMUMachine mips_magnum_machine = { From 5c63bcf7501527b844f61624957bdba254d75bfc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:52 +0100 Subject: [PATCH 03/14] jazz: remove usage of isa_mem_base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do assorted changes in memory-mapped rtc interface. Also fix size of ISA I/O memory region, which should be 0x10000 bytes. Signed-off-by: Hervé Poussineau Signed-off-by: Leon Alrae --- hw/mips/mips_jazz.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 738e9c73ec..ef5dd7d5ab 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -60,13 +60,16 @@ static void main_cpu_reset(void *opaque) static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) { - return cpu_inw(0x71); + uint8_t val; + address_space_read(&address_space_memory, 0x90000071, &val, 1); + return val; } static void rtc_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - cpu_outw(0x71, val & 0xff); + uint8_t buf = val & 0xff; + address_space_write(&address_space_memory, 0x90000071, &buf, 1); } static const MemoryRegionOps rtc_ops = { @@ -124,7 +127,6 @@ static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) { MemoryRegion *address_space = get_system_memory(); - MemoryRegion *address_space_io = get_system_io(); const char *cpu_model = machine->cpu_model; char *filename; int bios_size, n; @@ -134,7 +136,8 @@ static void mips_jazz_init(MachineState *machine, qemu_irq *rc4030, *i8259; rc4030_dma *dmas; void* rc4030_opaque; - MemoryRegion *isa = g_new(MemoryRegion, 1); + MemoryRegion *isa_mem = g_new(MemoryRegion, 1); + MemoryRegion *isa_io = g_new(MemoryRegion, 1); MemoryRegion *rtc = g_new(MemoryRegion, 1); MemoryRegion *i8042 = g_new(MemoryRegion, 1); MemoryRegion *dma_dummy = g_new(MemoryRegion, 1); @@ -219,8 +222,14 @@ static void mips_jazz_init(MachineState *machine, memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000); memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); + /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ + memory_region_init(isa_io, NULL, "isa-io", 0x00010000); + memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); + memory_region_add_subregion(address_space, 0x90000000, isa_io); + memory_region_add_subregion(address_space, 0x91000000, isa_mem); + isa_bus = isa_bus_new(NULL, isa_mem, isa_io); + /* ISA devices */ - isa_bus = isa_bus_new(NULL, get_system_memory(), address_space_io); i8259 = i8259_init(isa_bus, env->irq[4]); isa_bus_irqs(isa_bus, i8259); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); @@ -228,12 +237,6 @@ static void mips_jazz_init(MachineState *machine, pit = pit_init(isa_bus, 0x40, 0, NULL); pcspk_init(isa_bus, pit); - /* ISA IO space at 0x90000000 */ - memory_region_init_alias(isa, NULL, "isa_mmio", - get_system_io(), 0, 0x01000000); - memory_region_add_subregion(address_space, 0x90000000, isa); - isa_mem_base = 0x11000000; - /* Video card */ switch (jazz_model) { case JAZZ_MAGNUM: From 0c10962a033bfd4b6935389750e567eae18bd5e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:53 +0100 Subject: [PATCH 04/14] mips: remove isa_mem_base usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Hervé Poussineau Signed-off-by: Leon Alrae --- hw/mips/mips_r4k.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 5b982f2bde..3e90e273dc 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -165,7 +165,8 @@ void mips_r4k_init(MachineState *machine) MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios; MemoryRegion *iomem = g_new(MemoryRegion, 1); - MemoryRegion *isa = g_new(MemoryRegion, 1); + MemoryRegion *isa_io = g_new(MemoryRegion, 1); + MemoryRegion *isa_mem = g_new(MemoryRegion, 1); int bios_size; MIPSCPU *cpu; CPUMIPSState *env; @@ -267,20 +268,20 @@ void mips_r4k_init(MachineState *machine) cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); + /* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */ + memory_region_init_alias(isa_io, NULL, "isa-io", + get_system_io(), 0, 0x00010000); + memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); + memory_region_add_subregion(get_system_memory(), 0x14000000, isa_io); + memory_region_add_subregion(get_system_memory(), 0x10000000, isa_mem); + isa_bus = isa_bus_new(NULL, isa_mem, get_system_io()); + /* The PIC is attached to the MIPS CPU INT0 pin */ - isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io()); i8259 = i8259_init(isa_bus, env->irq[2]); isa_bus_irqs(isa_bus, i8259); rtc_init(isa_bus, 2000, NULL); - /* Register 64 KB of ISA IO space at 0x14000000 */ - memory_region_init_alias(isa, NULL, "isa_mmio", - get_system_io(), 0, 0x00010000); - memory_region_add_subregion(get_system_memory(), 0x14000000, isa); - - isa_mem_base = 0x10000000; - pit = pit_init(isa_bus, 0x40, 0, NULL); for(i = 0; i < MAX_SERIAL_PORTS; i++) { From cdba1415c159975c33776c386b934d6cb772421b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:54 +0100 Subject: [PATCH 05/14] piix4: use PCI address space instead of system memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit piix4 is only used on MIPS Malta board, which gives get_system_memory() to pci_register_bus(). Signed-off-by: Hervé Poussineau Signed-off-by: Leon Alrae --- hw/isa/piix4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 0cacc3bd3e..a9916df20a 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -86,7 +86,7 @@ static int piix4_initfn(PCIDevice *dev) { PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev); - isa_bus_new(DEVICE(d), get_system_memory(), + isa_bus_new(DEVICE(d), pci_address_space(dev), pci_address_space_io(dev)); piix4_dev = &d->dev; qemu_register_reset(piix4_reset, d); From f720f20350cfdf7e9d267947238cd2e5acee53f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:55 +0100 Subject: [PATCH 06/14] gt64xxx: remove isa_mem_base usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create a custom address space for PCI memory region and use it for the PCI bus. Dynamically handle PCI0 Mem0 and PCI0 Mem1 regions, as already done for PCI0 IO. Signed-off-by: Hervé Poussineau Signed-off-by: Leon Alrae --- hw/mips/gt64xxx_pci.c | 95 +++++++++++++++++++++++++++++++------------ 1 file changed, 68 insertions(+), 27 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 1f2fe5fab9..10fcca33f8 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -239,7 +239,11 @@ typedef struct GT64120State { uint32_t regs[GT_REGS]; PCI_MAPPING_ENTRY(PCI0IO); + PCI_MAPPING_ENTRY(PCI0M0); + PCI_MAPPING_ENTRY(PCI0M1); PCI_MAPPING_ENTRY(ISD); + MemoryRegion pci0_mem; + AddressSpace pci0_mem_as; } GT64120State; /* Adjust range to avoid touching space which isn't mappable via PCI */ @@ -290,25 +294,63 @@ static void gt64120_isd_mapping(GT64120State *s) static void gt64120_pci_mapping(GT64120State *s) { - /* Update IO mapping */ - if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) - { - /* Unmap old IO address */ - if (s->PCI0IO_length) - { - memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); - object_unparent(OBJECT(&s->PCI0IO_mem)); - } - /* Map new IO address */ - s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; - s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; - isa_mem_base = s->PCI0IO_start; - if (s->PCI0IO_length) { - memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio", - get_system_io(), 0, s->PCI0IO_length); - memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, - &s->PCI0IO_mem); - } + /* Update PCI0IO mapping */ + if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) { + /* Unmap old IO address */ + if (s->PCI0IO_length) { + memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); + object_unparent(OBJECT(&s->PCI0IO_mem)); + } + /* Map new IO address */ + s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; + s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - + (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; + if (s->PCI0IO_length) { + memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io", + get_system_io(), 0, s->PCI0IO_length); + memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, + &s->PCI0IO_mem); + } + } + + /* Update PCI0M0 mapping */ + if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) { + /* Unmap old MEM address */ + if (s->PCI0M0_length) { + memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem); + object_unparent(OBJECT(&s->PCI0M0_mem)); + } + /* Map new mem address */ + s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21; + s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) - + (s->regs[GT_PCI0M0LD] & 0x7f)) << 21; + if (s->PCI0M0_length) { + memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0", + &s->pci0_mem, s->PCI0M0_start, + s->PCI0M0_length); + memory_region_add_subregion(get_system_memory(), s->PCI0M0_start, + &s->PCI0M0_mem); + } + } + + /* Update PCI0M1 mapping */ + if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) { + /* Unmap old MEM address */ + if (s->PCI0M1_length) { + memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem); + object_unparent(OBJECT(&s->PCI0M1_mem)); + } + /* Map new mem address */ + s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21; + s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) - + (s->regs[GT_PCI0M1LD] & 0x7f)) << 21; + if (s->PCI0M1_length) { + memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1", + &s->pci0_mem, s->PCI0M1_start, + s->PCI0M1_length); + memory_region_add_subregion(get_system_memory(), s->PCI0M1_start, + &s->PCI0M1_mem); + } } } @@ -363,10 +405,12 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_PCI0M0LD: s->regs[GT_PCI0M0LD] = val & 0x00007fff; s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; + gt64120_pci_mapping(s); break; case GT_PCI0M1LD: s->regs[GT_PCI0M1LD] = val & 0x00007fff; s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; + gt64120_pci_mapping(s); break; case GT_PCI1IOLD: s->regs[GT_PCI1IOLD] = val & 0x00007fff; @@ -380,12 +424,12 @@ static void gt64120_writel (void *opaque, hwaddr addr, s->regs[GT_PCI1M1LD] = val & 0x00007fff; s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; break; + case GT_PCI0M0HD: + case GT_PCI0M1HD: case GT_PCI0IOHD: s->regs[saddr] = val & 0x0000007f; gt64120_pci_mapping(s); break; - case GT_PCI0M0HD: - case GT_PCI0M1HD: case GT_PCI1IOHD: case GT_PCI1M0HD: case GT_PCI1M1HD: @@ -1124,10 +1168,12 @@ PCIBus *gt64120_register(qemu_irq *pic) qdev_init_nofail(dev); d = GT64120_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); + memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX); + address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); phb->bus = pci_register_bus(dev, "pci", gt64120_pci_set_irq, gt64120_pci_map_irq, pic, - get_system_memory(), + &d->pci0_mem, get_system_io(), PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000); @@ -1142,11 +1188,6 @@ static int gt64120_init(SysBusDevice *dev) s = GT64120_PCI_HOST_BRIDGE(dev); - /* FIXME: This value is computed from registers during reset, but some - devices (e.g. VGA card) need to know it when they are registered. - This also mean that changing the register to change the mapping - does not fully work. */ - isa_mem_base = 0x10000000; qemu_register_reset(gt64120_reset, s); return 0; } From b19c1c08de4365df90207862f4f9f7c1cd512bd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:56 +0100 Subject: [PATCH 07/14] isa: remove isa_mem_base variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that isa_mem_base variable is always 0, we can remove its usage. Signed-off-by: Hervé Poussineau Signed-off-by: Leon Alrae --- hw/display/cirrus_vga.c | 2 +- hw/display/vga-isa.c | 2 +- hw/display/vga.c | 3 +-- hw/isa/isa-bus.c | 1 - include/hw/isa/isa.h | 2 -- 5 files changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index 3a53f20392..ec923c8c4b 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -2907,7 +2907,7 @@ static void cirrus_init_common(CirrusVGAState *s, Object *owner, bank, 1); } memory_region_add_subregion_overlap(system_memory, - isa_mem_base + 0x000a0000, + 0x000a0000, &s->low_mem_container, 1); memory_region_set_coalescing(&s->low_mem); diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c index 2b480bd44d..7f3c98941b 100644 --- a/hw/display/vga-isa.c +++ b/hw/display/vga-isa.c @@ -64,7 +64,7 @@ static void vga_isa_realizefn(DeviceState *dev, Error **errp) isa_register_portio_list(isadev, 0x1ce, vbe_ports, s, "vbe"); } memory_region_add_subregion_overlap(isa_address_space(isadev), - isa_mem_base + 0x000a0000, + 0x000a0000, vga_io_memory, 1); memory_region_set_coalescing(vga_io_memory); s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s); diff --git a/hw/display/vga.c b/hw/display/vga.c index 9c62fbf488..c8c49abc6e 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -177,7 +177,6 @@ static void vga_update_memory_access(VGACommonState *s) size = 0x8000; break; } - base += isa_mem_base; memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram), "vga.chain4", &s->vram, offset, size); memory_region_add_subregion_overlap(s->legacy_address_space, base, @@ -2218,7 +2217,7 @@ void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space, vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports); memory_region_add_subregion_overlap(address_space, - isa_mem_base + 0x000a0000, + 0x000a0000, vga_io_memory, 1); memory_region_set_coalescing(vga_io_memory); diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c index fd6a3a19e7..825aa627df 100644 --- a/hw/isa/isa-bus.c +++ b/hw/isa/isa-bus.c @@ -23,7 +23,6 @@ #include "hw/isa/isa.h" static ISABus *isabus; -hwaddr isa_mem_base = 0; static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent); static char *isabus_get_fw_dev_path(DeviceState *dev); diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index c6218224d5..cf7bd343c7 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -99,8 +99,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d) return ISA_BUS(qdev_get_parent_bus(DEVICE(d))); } -extern hwaddr isa_mem_base; - /* dma.c */ int DMA_get_channel_mode (int nchan); int DMA_read_memory (int nchan, void *buf, int pos, int size); From 196a7958c65778d05a491309377a65c58f643a1c Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sat, 20 Dec 2014 23:00:25 +0000 Subject: [PATCH 08/14] target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors Signed-off-by: Maciej W. Rozycki Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 1543f6c388..9e8433a919 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -474,7 +474,7 @@ static const mips_def_t mips_defs[] = .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, - .CP0_Status_rw_bitmask = 0x32F8FFFF, + .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 36, .insn_flags = CPU_MIPS64, @@ -575,7 +575,7 @@ static const mips_def_t mips_defs[] = .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, - .CP0_Status_rw_bitmask = 0x32F8FFFF, + .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 36, .insn_flags = CPU_MIPS64R2, From fe2372910a09034591fd2cfc2d70cca43fccaa95 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Mon, 26 Jan 2015 15:53:16 +0000 Subject: [PATCH 09/14] target-mips: fix detection of the end of the page during translation The test is supposed to terminate TB if the end of the page is reached. However, with current implementation it may never succeed for microMIPS or mips16. Reported-by: Richard Henderson Signed-off-by: Leon Alrae Reviewed-by: Maciej W. Rozycki Reviewed-by: Richard Henderson --- target-mips/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 881e7fb6d6..a24863c09f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19095,6 +19095,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, CPUMIPSState *env = &cpu->env; DisasContext ctx; target_ulong pc_start; + target_ulong next_page_start; CPUBreakpoint *bp; int j, lj = -1; int num_insns; @@ -19106,6 +19107,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, qemu_log("search pc %d\n", search_pc); pc_start = tb->pc; + next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; ctx.pc = pc_start; ctx.saved_pc = -1; ctx.singlestep_enabled = cs->singlestep_enabled; @@ -19204,8 +19206,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, break; } - if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) + if (ctx.pc >= next_page_start) { break; + } if (tcg_op_buf_full()) { break; From 6489dd250a4d6e86ecbb4badf82cc102afe26f33 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Mon, 26 Jan 2015 16:06:43 +0000 Subject: [PATCH 10/14] target-mips: ll and lld cause AdEL exception for unaligned address Signed-off-by: Leon Alrae Reviewed-by: Maciej W. Rozycki --- target-mips/op_helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index ea7d95f36c..73a8e458fc 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -304,16 +304,20 @@ static inline hwaddr do_translate_address(CPUMIPSState *env, } } -#define HELPER_LD_ATOMIC(name, insn) \ +#define HELPER_LD_ATOMIC(name, insn, almask) \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ { \ + if (arg & almask) { \ + env->CP0_BadVAddr = arg; \ + helper_raise_exception(env, EXCP_AdEL); \ + } \ env->lladdr = do_translate_address(env, arg, 0); \ env->llval = do_##insn(env, arg, mem_idx); \ return env->llval; \ } -HELPER_LD_ATOMIC(ll, lw) +HELPER_LD_ATOMIC(ll, lw, 0x3) #ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ld) +HELPER_LD_ATOMIC(lld, ld, 0x7) #endif #undef HELPER_LD_ATOMIC From d3b1979d7b37c7fa6b187442e0990afa6f88fe3b Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Mon, 26 Jan 2015 16:17:39 +0000 Subject: [PATCH 11/14] target-mips: use CP0EnLo_XI instead of magic number Signed-off-by: Leon Alrae Reviewed-by: Maciej W. Rozycki --- target-mips/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index a24863c09f..b80af98593 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4947,7 +4947,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) #if defined(TARGET_MIPS64) if (ctx->rxi) { TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << 62)); + tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); tcg_gen_shri_tl(tmp, tmp, 32); tcg_gen_or_tl(arg, arg, tmp); tcg_temp_free(tmp); @@ -5002,7 +5002,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) #if defined(TARGET_MIPS64) if (ctx->rxi) { TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << 62)); + tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); tcg_gen_shri_tl(tmp, tmp, 32); tcg_gen_or_tl(arg, arg, tmp); tcg_temp_free(tmp); From b40a1530f294b5fa4479dc3ca9bf46c269d08d87 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Mon, 26 Jan 2015 16:49:42 +0000 Subject: [PATCH 12/14] target-mips: fix broken snapshotting Recently added CP0.BadInstr and CP0.BadInstrP registers ended up in cpu_load() under different offset than in cpu_save(). These and all registers between were incorrectly restored. Signed-off-by: Leon Alrae --- target-mips/machine.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target-mips/machine.c b/target-mips/machine.c index 0ba7d736db..6c76dfbe03 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -285,6 +285,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_sbe32s(f, &env->CP0_SRSConf4); qemu_get_sbe32s(f, &env->CP0_HWREna); qemu_get_betls(f, &env->CP0_BadVAddr); + if (version_id >= 5) { + qemu_get_be32s(f, &env->CP0_BadInstr); + qemu_get_be32s(f, &env->CP0_BadInstrP); + } qemu_get_sbe32s(f, &env->CP0_Count); qemu_get_betls(f, &env->CP0_EntryHi); qemu_get_sbe32s(f, &env->CP0_Compare); @@ -319,8 +323,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) qemu_get_betls(f, &env->CP0_ErrorEPC); qemu_get_sbe32s(f, &env->CP0_DESAVE); if (version_id >= 5) { - qemu_get_be32s(f, &env->CP0_BadInstr); - qemu_get_be32s(f, &env->CP0_BadInstrP); for (i = 0; i < MIPS_KSCRATCH_NUM; i++) { qemu_get_betls(f, &env->CP0_KScratch[i]); } From 5e88759a52934a32502298f2c78c6dfaa144364b Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Mon, 26 Jan 2015 16:58:57 +0000 Subject: [PATCH 13/14] target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction Using rs = -1 in gen_logic_imm() for microMIPS LUI instruction is dangerous and may bite us when implementing microMIPS R6 because in R6 AUI and LUI are distinguished by rs value. Therefore use 0 for safety. Reported-by: Paolo Bonzini Signed-off-by: Leon Alrae --- target-mips/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index b80af98593..ca51149872 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -13653,7 +13653,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, target. */ break; case LUI: - gen_logic_imm(ctx, OPC_LUI, rs, -1, imm); + gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); break; case SYNCI: /* Break the TB to be able to sync copied instructions From 1ab2aea2489f34a05dabfe5bd91a76d89dd8c922 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Fri, 30 Jan 2015 15:08:05 +0000 Subject: [PATCH 14/14] linux-user: correct stat structure in MIPS N32 Simple "hello world" MIPS N32 userland program crashes with segfault due to incorrectly defined stat structure in QEMU. Correct "target_stat" definition to match kernel's "stat64" as in MIPS N32 there are only plain "stat" syscalls using 64-bit structure. Reported-by: Daniel Sanders Signed-off-by: Leon Alrae Tested-by: Daniel Sanders Reviewed-by: James Hogan --- linux-user/syscall_defs.h | 86 +++++++++------------------------------ 1 file changed, 19 insertions(+), 67 deletions(-) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 9ed6de88ec..edd5f3c80b 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1607,73 +1607,25 @@ struct target_stat { #elif defined(TARGET_ABI_MIPSN32) struct target_stat { - unsigned st_dev; - int st_pad1[3]; /* Reserved for network id */ - unsigned int st_ino; - unsigned int st_mode; - unsigned int st_nlink; - int st_uid; - int st_gid; - unsigned st_rdev; - unsigned int st_pad2[2]; - unsigned int st_size; - unsigned int st_pad3; - /* - * Actually this should be timestruc_t st_atime, st_mtime and st_ctime - * but we don't have it under Linux. - */ - unsigned int target_st_atime; - unsigned int target_st_atime_nsec; - unsigned int target_st_mtime; - unsigned int target_st_mtime_nsec; - unsigned int target_st_ctime; - unsigned int target_st_ctime_nsec; - unsigned int st_blksize; - unsigned int st_blocks; - unsigned int st_pad4[14]; -}; - -/* - * This matches struct stat64 in glibc2.1, hence the absolutely insane - * amounts of padding around dev_t's. The memory layout is the same as of - * struct stat of the 64-bit kernel. - */ - -#define TARGET_HAS_STRUCT_STAT64 -struct target_stat64 { - unsigned int st_dev; - unsigned int st_pad0[3]; /* Reserved for st_dev expansion */ - - target_ulong st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - int st_uid; - int st_gid; - - unsigned int st_rdev; - unsigned int st_pad1[3]; /* Reserved for st_rdev expansion */ - - int st_size; - - /* - * Actually this should be timestruc_t st_atime, st_mtime and st_ctime - * but we don't have it under Linux. - */ - int target_st_atime; - unsigned int target_st_atime_nsec; /* Reserved for st_atime expansion */ - - int target_st_mtime; - unsigned int target_st_mtime_nsec; /* Reserved for st_mtime expansion */ - - int target_st_ctime; - unsigned int target_st_ctime_nsec; /* Reserved for st_ctime expansion */ - - unsigned int st_blksize; - unsigned int st_pad2; - - int st_blocks; + abi_ulong st_dev; + abi_ulong st_pad0[3]; /* Reserved for st_dev expansion */ + uint64_t st_ino; + unsigned int st_mode; + unsigned int st_nlink; + int st_uid; + int st_gid; + abi_ulong st_rdev; + abi_ulong st_pad1[3]; /* Reserved for st_rdev expansion */ + int64_t st_size; + abi_long target_st_atime; + abi_ulong target_st_atime_nsec; /* Reserved for st_atime expansion */ + abi_long target_st_mtime; + abi_ulong target_st_mtime_nsec; /* Reserved for st_mtime expansion */ + abi_long target_st_ctime; + abi_ulong target_st_ctime_nsec; /* Reserved for st_ctime expansion */ + abi_ulong st_blksize; + abi_ulong st_pad2; + int64_t st_blocks; }; #elif defined(TARGET_ABI_MIPSO32)