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target/ppc: Move mffscrn[i] to decodetree

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Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220629162904.105060-3-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Víctor Colombo 2022-06-29 13:28:55 -03:00 committed by Daniel Henrique Barboza
parent bbecdb22ae
commit bf8adfd88b
4 changed files with 51 additions and 49 deletions
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8
target/ppc/insn32.decode
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@ -124,6 +124,9 @@
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 . l:1 ra:5 rb:5 .......... . &X_bfl
&X_imm2 rt imm
@X_imm2 ...... rt:5 ..... ... imm:2 .......... . &X_imm2
%x_xt 0:1 21:5
&X_imm5 xt imm:uint8_t vrb
@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5 xt=%x_xt
@ -334,6 +337,11 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
### Move To/From FPSCR
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
### Decimal Floating-Point Arithmetic Instructions
DADD 111011 ..... ..... ..... 0000000010 . @X_rc

3
target/ppc/internal.h
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@ -159,9 +159,6 @@ EXTRACT_HELPER(FPL, 25, 1);
EXTRACT_HELPER(FPFLM, 17, 8);
EXTRACT_HELPER(FPW, 16, 1);
/* mffscrni */
EXTRACT_HELPER(RM, 11, 2);
/* addpcis */
EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
#if defined(TARGET_PPC64)

85
target/ppc/translate/fp-impl.c.inc
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@ -685,71 +685,72 @@ static void gen_mffsce(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i32 mask = tcg_const_i32(0x0001);
TCGv_i64 fpscr = tcg_temp_new_i64();
TCGv_i64 fpscr_masked = tcg_temp_new_i64();
gen_reset_fpstatus();
tcg_gen_extu_tl_i64(t0, cpu_fpscr);
tcg_gen_andi_i64(t0, t0, FP_DRN | FP_ENABLES | FP_RN);
set_fpr(rD(ctx->opcode), t0);
tcg_gen_extu_tl_i64(fpscr, cpu_fpscr);
tcg_gen_andi_i64(fpscr_masked, fpscr, mask);
set_fpr(rt, fpscr_masked);
/* Mask FPSCR value to clear RN. */
tcg_gen_andi_i64(t0, t0, ~FP_RN);
tcg_temp_free_i64(fpscr_masked);
/* Merge RN into FPSCR value. */
tcg_gen_or_i64(t0, t0, t1);
gen_helper_store_fpscr(cpu_env, t0, mask);
tcg_temp_free_i32(mask);
tcg_temp_free_i64(t0);
return fpscr;
}
/* mffscrn */
static void gen_mffscrn(DisasContext *ctx)
static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask,
TCGv_i64 set_mask, uint32_t store_mask)
{
TCGv_i64 t1;
TCGv_i64 fpscr_masked = tcg_temp_new_i64();
TCGv_i32 st_mask = tcg_constant_i32(store_mask);
if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return gen_mffs(ctx);
}
tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask);
tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask);
gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask);
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
tcg_temp_free_i64(fpscr_masked);
}
static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a)
{
TCGv_i64 t1, fpscr;
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);
t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
/* Mask FRB to get just RN. */
get_fpr(t1, a->rb);
tcg_gen_andi_i64(t1, t1, FP_RN);
gen_helper_mffscrn(ctx, t1);
gen_reset_fpstatus();
fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
store_fpscr_masked(fpscr, FP_RN, t1, 0x0001);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(fpscr);
return true;
}
/* mffscrni */
static void gen_mffscrni(DisasContext *ctx)
static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a)
{
TCGv_i64 t1;
TCGv_i64 t1, fpscr;
if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
return gen_mffs(ctx);
}
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_FPU(ctx);
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
t1 = tcg_temp_new_i64();
tcg_gen_movi_i64(t1, a->imm);
t1 = tcg_const_i64((uint64_t)RM(ctx->opcode));
gen_helper_mffscrn(ctx, t1);
gen_reset_fpstatus();
fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
store_fpscr_masked(fpscr, FP_RN, t1, 0x0001);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(fpscr);
return true;
}
/* mtfsb0 */

4
target/ppc/translate/fp-ops.c.inc
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@ -79,10 +79,6 @@ GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,
PPC_NONE),
GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT,
PPC_NONE),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),