hw/arm/fsl-imx25: Wire up eSDHC controllers
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives provided on the command line to available eSDHC controllers. This patch enables booting the imx25-pdk emulation from SD card. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200310215146.19688-2-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: made commit subject consistent with other patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -31,6 +31,8 @@
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#include "hw/qdev-properties.h"
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#include "chardev/char.h"
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#define IMX25_ESDHC_CAPABILITIES 0x07e20000
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static void fsl_imx25_init(Object *obj)
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{
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FslIMX25State *s = FSL_IMX25(obj);
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@ -74,6 +76,11 @@ static void fsl_imx25_init(Object *obj)
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sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
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TYPE_IMX_GPIO);
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}
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for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
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sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdhc[i]),
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TYPE_IMX_USDHC);
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}
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}
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static void fsl_imx25_realize(DeviceState *dev, Error **errp)
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@ -246,6 +253,31 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
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gpio_table[i].irq));
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}
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/* Initialize all SDHC */
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for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
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{ FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
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{ FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
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};
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object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
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&err);
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object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
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"capareg", &err);
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object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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esdhc_table[i].irq));
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}
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/* initialize 2 x 16 KB ROM */
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memory_region_init_rom(&s->rom[0], NULL,
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"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
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@ -26,6 +26,7 @@
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/qdev-properties.h"
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#include "hw/arm/fsl-imx25.h"
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#include "hw/boards.h"
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#include "qemu/error-report.h"
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@ -120,6 +121,21 @@ static void imx25_pdk_init(MachineState *machine)
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imx25_pdk_binfo.board_id = 1771,
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imx25_pdk_binfo.nb_cpus = 1;
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for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
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BusState *bus;
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DeviceState *carddev;
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DriveInfo *di;
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BlockBackend *blk;
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di = drive_get_next(IF_SD);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
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carddev = qdev_create(bus, TYPE_SD_CARD);
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qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
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object_property_set_bool(OBJECT(carddev), true,
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"realized", &error_fatal);
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}
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/*
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* We test explicitly for qtest here as it is not done (yet?) in
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* arm_load_kernel(). Without this the "make check" command would
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@ -27,6 +27,7 @@
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#include "hw/misc/imx_rngc.h"
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#include "hw/i2c/imx_i2c.h"
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#include "hw/gpio/imx_gpio.h"
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#include "hw/sd/sdhci.h"
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#include "exec/memory.h"
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#include "target/arm/cpu.h"
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@ -38,6 +39,7 @@
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#define FSL_IMX25_NUM_EPITS 2
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#define FSL_IMX25_NUM_I2CS 3
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#define FSL_IMX25_NUM_GPIOS 4
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#define FSL_IMX25_NUM_ESDHCS 2
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typedef struct FslIMX25State {
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/*< private >*/
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@ -54,6 +56,7 @@ typedef struct FslIMX25State {
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IMXRNGCState rngc;
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IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
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IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
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SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
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MemoryRegion rom[2];
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MemoryRegion iram;
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MemoryRegion iram_alias;
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@ -215,6 +218,10 @@ typedef struct FslIMX25State {
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#define FSL_IMX25_GPIO3_SIZE 0x4000
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#define FSL_IMX25_RNGC_ADDR 0x53FB0000
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#define FSL_IMX25_RNGC_SIZE 0x4000
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#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
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#define FSL_IMX25_ESDHC1_SIZE 0x4000
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#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
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#define FSL_IMX25_ESDHC2_SIZE 0x4000
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#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
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#define FSL_IMX25_GPIO1_SIZE 0x4000
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#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
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@ -250,5 +257,7 @@ typedef struct FslIMX25State {
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#define FSL_IMX25_GPIO2_IRQ 51
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#define FSL_IMX25_GPIO3_IRQ 16
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#define FSL_IMX25_GPIO4_IRQ 23
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#define FSL_IMX25_ESDHC1_IRQ 9
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#define FSL_IMX25_ESDHC2_IRQ 8
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#endif /* FSL_IMX25_H */
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