e2k: Fix read and write probe access.
Signed-off-by: Denis Drakhnya <numas13@gmail.com>
This commit is contained in:
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6cbcdc4d5c
commit
c03d91b7c0
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@ -19,11 +19,11 @@ DEF_HELPER_1(signal_return, void, env)
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DEF_HELPER_4(setwd, void, env, int, int, int)
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DEF_HELPER_FLAGS_2(probe_read_access, TCG_CALL_NO_RWG, int, env, tl)
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DEF_HELPER_FLAGS_2(probe_write_access, TCG_CALL_NO_RWG, int, env, tl)
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DEF_HELPER_FLAGS_4(probe_read_access, TCG_CALL_NO_RWG, int, env, tl, int, int)
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DEF_HELPER_FLAGS_4(probe_write_access, TCG_CALL_NO_RWG, int, env, tl, int, int)
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DEF_HELPER_1(aau_load_program, void, env)
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DEF_HELPER_4(mova_ptr, tl, env, int, int, int)
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DEF_HELPER_6(mova_ptr, tl, env, int, int, int, int, int)
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DEF_HELPER_3(aau_am, void, env, int, int)
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DEF_HELPER_4(dam_lock_addr, void, env, i64, int, int)
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DEF_HELPER_4(dam_unlock_addr, int, env, i64, int, int)
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@ -45,7 +45,8 @@ void HELPER(aau_load_program)(CPUE2KState *env)
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}
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}
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target_ulong HELPER(mova_ptr)(CPUE2KState *env, int chan, int area, int ind)
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target_ulong HELPER(mova_ptr)(CPUE2KState *env, int chan, int area, int ind,
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int size, int mmu_idx)
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{
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E2KAauPrefState *ps = chan < 2 ? &env->aau.pl : &env->aau.pr;
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E2KAauAreaState *as = &ps->area[area];
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@ -55,7 +56,7 @@ target_ulong HELPER(mova_ptr)(CPUE2KState *env, int chan, int area, int ind)
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target_ulong page = ptr & ~(TARGET_PAGE_SIZE - 1);
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if (as->last_page == 0 || page != as->last_page) {
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if (!helper_probe_read_access(env, page)) {
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if (!helper_probe_read_access(env, ptr, size, mmu_idx)) {
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return 0;
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}
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as->last_page = page;
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@ -5,22 +5,35 @@
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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int HELPER(probe_read_access)(CPUE2KState *env, target_ulong addr)
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static int e2k_probe_access(CPUE2KState *env, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx)
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{
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target_ulong addr_end = addr + size;
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int flags;
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void *ignore;
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flags = probe_access_flags(env, addr, MMU_DATA_LOAD, 0, true, &ignore, 0);
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flags = probe_access_flags(env, addr, access_type, mmu_idx,
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true, &ignore, 0);
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return (flags & TLB_INVALID_MASK) == 0;
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if (flags & TLB_INVALID_MASK) {
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return 0;
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} else if ((addr & ~TARGET_PAGE_MASK) != (addr_end & ~TARGET_PAGE_MASK)) {
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flags = probe_access_flags(env, addr_end, access_type, mmu_idx,
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true, &ignore, 0);
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return !(flags & TLB_INVALID_MASK);
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}
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return 1;
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}
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int HELPER(probe_write_access)(CPUE2KState *env, target_ulong addr)
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int HELPER(probe_read_access)(CPUE2KState *env, target_ulong addr,
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int size, int mmu_idx)
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{
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int flags;
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void *ignore;
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flags = probe_access_flags(env, addr, MMU_DATA_STORE, 0, true, &ignore, 0);
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return (flags & TLB_INVALID_MASK) == 0;
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return e2k_probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx);
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}
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int HELPER(probe_write_access)(CPUE2KState *env, target_ulong addr,
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int size, int mmu_idx)
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{
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return e2k_probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx);
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}
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@ -3672,6 +3672,30 @@ static MemOp scan_st_mas(Instr *instr, MemOp memop, bool *skip, bool *check)
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return memop;
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}
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static void gen_probe_read_access(TCGv_i32 ret, TCGv addr, int size,
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int mmu_idx)
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{
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TCGv_i32 t0 = tcg_const_i32(size);
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TCGv_i32 t1 = tcg_const_i32(mmu_idx);
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gen_helper_probe_read_access(ret, cpu_env, addr, t0, t1);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t0);
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}
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static void gen_probe_write_access(TCGv_i32 ret, TCGv addr, int size,
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int mmu_idx)
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{
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TCGv_i32 t0 = tcg_const_i32(size);
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TCGv_i32 t1 = tcg_const_i32(mmu_idx);
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gen_helper_probe_write_access(ret, cpu_env, addr, t0, t1);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t0);
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}
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static void gen_ld_raw_i64(Instr *instr, TCGv_i32 tag, TCGv addr,
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MemOp memop, bool skip, bool save)
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{
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@ -3682,7 +3706,7 @@ static void gen_ld_raw_i64(Instr *instr, TCGv_i32 tag, TCGv addr,
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TCGLabel *l1 = gen_new_label();
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TCGv_i32 t0 = tcg_temp_new_i32();
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gen_helper_probe_read_access(t0, cpu_env, addr);
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gen_probe_read_access(t0, addr, memop_size(memop), instr->ctx->mmuidx);
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tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
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/* address is not available */
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@ -3742,7 +3766,7 @@ static void gen_ld_raw_i128(Instr *instr, TCGv_i32 tag, TCGv addr,
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TCGLabel *l1 = gen_new_label();
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TCGv_i32 t3 = tcg_temp_new_i32();
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gen_helper_probe_read_access(t3, cpu_env, addr);
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gen_probe_read_access(t3, addr, 16, instr->ctx->mmuidx);
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tcg_gen_brcondi_i32(TCG_COND_NE, t3, 0, l1);
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/* address is not available */
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@ -3851,7 +3875,8 @@ static void gen_atomic_cmpxchg_i32(Instr *instr, TCGv_i32 value, TCGv addr,
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if (instr->sm) { \
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TCGv_i32 t0 = tcg_temp_new_i32(); \
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\
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gen_helper_probe_write_access(t0, cpu_env, addr); \
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gen_probe_write_access(t0, addr, memop_size(memop), \
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instr->ctx->mmuidx); \
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tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l0); \
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\
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tcg_temp_free_i32(t0); \
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@ -3904,7 +3929,7 @@ static void gen_st_raw_i128(Instr *instr, TCGv addr,
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if (instr->sm) {
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TCGv_i32 t0 = tcg_temp_new_i32();
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gen_helper_probe_write_access(t0, cpu_env, addr);
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gen_probe_write_access(t0, addr, 16, instr->ctx->mmuidx);
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tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l0);
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tcg_temp_free_i32(t0);
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@ -3985,7 +4010,7 @@ static void gen_stm_raw_i128(Instr *instr, TCGv addr,
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if (instr->sm) {
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TCGv_i32 t0 = tcg_temp_new_i32();
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gen_helper_probe_write_access(t0, cpu_env, addr);
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gen_probe_write_access(t0, addr, 16, instr->ctx->mmuidx);
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tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l0);
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tcg_temp_free_i32(t0);
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@ -4349,7 +4374,7 @@ static void gen_staaqp(Instr *instr)
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if (instr->sm) {
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TCGv_i32 t1 = tcg_temp_new_i32();
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gen_helper_probe_write_access(t1, cpu_env, t0);
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gen_probe_write_access(t1, t0, 16, instr->ctx->mmuidx);
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tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l0);
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tcg_temp_free_i32(t1);
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}
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@ -4403,7 +4428,7 @@ static void gen_staa_i64(Instr *instr)
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if (instr->sm) {
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TCGv_i32 t1 = tcg_temp_new_i32();
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gen_helper_probe_write_access(t1, cpu_env, t0);
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gen_probe_write_access(t1, t0, memop_size(memop), instr->ctx->mmuidx);
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tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l0);
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tcg_temp_free_i32(t1);
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}
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@ -4457,7 +4482,7 @@ static void gen_staa_i32(Instr *instr, MemOp memop)
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if (instr->sm) {
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TCGv_i32 t1 = tcg_temp_new_i32();
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gen_helper_probe_write_access(t1, cpu_env, t0);
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gen_probe_write_access(t1, t0, memop_size(memop), instr->ctx->mmuidx);
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tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l0);
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tcg_temp_free_i32(t1);
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}
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@ -6784,12 +6809,17 @@ static void gen_checked_ld_qp(DisasContext *ctx, Mova *instr, TCGv addr)
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tagged_free_ptr(r);
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}
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static inline void gen_mova_ptr(TCGv ret, Mova *instr)
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static void gen_mova_ptr(TCGv ret, Mova *instr, int size, int mmu_idx)
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{
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TCGv_i32 t0 = tcg_const_i32(instr->chan);
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TCGv_i32 t1 = tcg_const_i32(instr->area);
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TCGv_i32 t2 = tcg_const_i32(instr->ind);
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gen_helper_mova_ptr(ret, cpu_env, t0, t1, t2);
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TCGv_i32 t3 = tcg_const_i32(size);
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TCGv_i32 t4 = tcg_const_i32(mmu_idx);
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gen_helper_mova_ptr(ret, cpu_env, t0, t1, t2, t3, t4);
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tcg_temp_free_i32(t4);
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tcg_temp_free_i32(t3);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t0);
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@ -6803,19 +6833,20 @@ static void gen_mova(DisasContext *ctx, Mova *instr)
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ctx->aau_am[instr->chan] = instr->am ? instr->area : -1;
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// TODO: check ind has proper alignment
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// TODO: check ind is less than mrng
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gen_mova_ptr(t0, instr);
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switch(instr->opc) {
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case 1: /* movab */
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case 2: /* movah */
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case 3: /* movaw */
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case 4: /* movad */
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gen_mova_ptr(t0, instr, 1 << (instr->opc - 1), ctx->mmuidx);
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gen_checked_ld(ctx, instr, t0);
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break;
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case 5: /* movaq */
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e2k_todo_illop(ctx, "movaq");
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break;
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case 7: /* movaqp */
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gen_mova_ptr(t0, instr, 16, ctx->mmuidx);
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gen_checked_ld_qp(ctx, instr, t0);
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break;
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default:
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