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pcie: Support PCIe Gen5/Gen6 link speeds

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This patch extends the PCIe link speed option so that slots can be
configured as supporting 32GT/s (Gen5) or 64GT/s (Gen5) speeds.
This is as simple as setting the appropriate bit in LnkCap2 and
the appropriate value in LnkCap and LnkCtl2.

Signed-off-by: Lukas Stockner <lstockner@genesiscloud.com>
Message-Id: <20240215012326.3272366-1-lstockner@genesiscloud.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Lukas Stockner 2024-02-15 02:23:26 +01:00 committed by Michael S. Tsirkin
parent 52767e1063
commit c08da86dc4
4 changed files with 29 additions and 3 deletions
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16
hw/core/qdev-properties-system.c
View File

@ -955,7 +955,7 @@ const PropertyInfo qdev_prop_off_auto_pcibar = {
.set_default_value = qdev_propinfo_set_default_value_enum,
};
/* --- PCIELinkSpeed 2_5/5/8/16 -- */
/* --- PCIELinkSpeed 2_5/5/8/16/32/64 -- */
static void get_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
@ -977,6 +977,12 @@ static void get_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name,
case QEMU_PCI_EXP_LNK_16GT:
speed = PCIE_LINK_SPEED_16;
break;
case QEMU_PCI_EXP_LNK_32GT:
speed = PCIE_LINK_SPEED_32;
break;
case QEMU_PCI_EXP_LNK_64GT:
speed = PCIE_LINK_SPEED_64;
break;
default:
/* Unreachable */
abort();
@ -1010,6 +1016,12 @@ static void set_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name,
case PCIE_LINK_SPEED_16:
*p = QEMU_PCI_EXP_LNK_16GT;
break;
case PCIE_LINK_SPEED_32:
*p = QEMU_PCI_EXP_LNK_32GT;
break;
case PCIE_LINK_SPEED_64:
*p = QEMU_PCI_EXP_LNK_64GT;
break;
default:
/* Unreachable */
abort();
@ -1018,7 +1030,7 @@ static void set_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name,
const PropertyInfo qdev_prop_pcie_link_speed = {
.name = "PCIELinkSpeed",
.description = "2_5/5/8/16",
.description = "2_5/5/8/16/32/64",
.enum_table = &PCIELinkSpeed_lookup,
.get = get_prop_pcielinkspeed,
.set = set_prop_pcielinkspeed,

8
hw/pci/pcie.c
View File

@ -153,6 +153,14 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
PCI_EXP_LNKCAP2_SLS_16_0GB);
}
if (s->speed > QEMU_PCI_EXP_LNK_16GT) {
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
PCI_EXP_LNKCAP2_SLS_32_0GB);
}
if (s->speed > QEMU_PCI_EXP_LNK_32GT) {
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
PCI_EXP_LNKCAP2_SLS_64_0GB);
}
}
}

2
include/hw/pci/pcie_regs.h
View File

@ -39,6 +39,8 @@ typedef enum PCIExpLinkSpeed {
QEMU_PCI_EXP_LNK_5GT,
QEMU_PCI_EXP_LNK_8GT,
QEMU_PCI_EXP_LNK_16GT,
QEMU_PCI_EXP_LNK_32GT,
QEMU_PCI_EXP_LNK_64GT,
} PCIExpLinkSpeed;
#define QEMU_PCI_EXP_LNKCAP_MLS(speed) (speed)

6
qapi/common.json
View File

@ -107,10 +107,14 @@
#
# @16: 16.0GT/s
#
# @32: 32.0GT/s
#
# @64: 64.0GT/s
#
# Since: 4.0
##
{ 'enum': 'PCIELinkSpeed',
'data': [ '2_5', '5', '8', '16' ] }
'data': [ '2_5', '5', '8', '16', '32', '64' ] }
##
# @PCIELinkWidth: