OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/mips: Convert to 3-phase reset 

Convert the mips CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-id: 20221124115023.2437291-11-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-24 11:50:13 +00:00
parent d4bc6c1a79
commit c08dfb7ae2
2 changed files with 10 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/mips/cpu-qom.h
View File

@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/** /**
* MIPSCPUClass: * MIPSCPUClass:
* @parent_realize: The parent class' realize handler. * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_phases: The parent class' reset phase handlers.
* *
* A MIPS CPU model. * A MIPS CPU model.
*/ */
@ -44,7 +44,7 @@ struct MIPSCPUClass {
/*< public >*/ /*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
const struct mips_def_t *cpu_def; const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */

12
target/mips/cpu.c
View File

@ -182,14 +182,16 @@ static bool mips_cpu_has_work(CPUState *cs)
#include "cpu-defs.c.inc" #include "cpu-defs.c.inc"
static void mips_cpu_reset(DeviceState *dev) static void mips_cpu_reset_hold(Object *obj)
{ {
CPUState *cs = CPU(dev); CPUState *cs = CPU(obj);
MIPSCPU *cpu = MIPS_CPU(cs); MIPSCPU *cpu = MIPS_CPU(cs);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
CPUMIPSState *env = &cpu->env; CPUMIPSState *env = &cpu->env;
mcc->parent_reset(dev); if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
@ -562,10 +564,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, mips_cpu_realizefn, device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize); &mcc->parent_realize);
device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = mips_cpu_class_by_name; cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work; cc->has_work = mips_cpu_has_work;