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qemu-macppc updates 

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20210113' into staging

qemu-macppc updates

# gpg: Signature made Wed 13 Jan 2021 13:02:20 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-macppc-20210113:
  macio: don't set user_creatable to false
  macio: wire macio GPIOs to OpenPIC using sysbus IRQs
  macio: move OpenPIC inside macio-newworld device
  mac_newworld: delay wiring of PCI IRQs in New World machine
  macio: move heathrow PIC inside macio-oldworld device
  mac_oldworld: move initialisation of grackle before heathrow
  mac_oldworld: remove duplicate bus check for PPC_INPUT(env)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-01-13 19:18:28 +00:00
parent 45240eed4f 7b3180f911
commit c0dd6654f2
6 changed files with 104 additions and 126 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
hw/misc/macio/gpio.c
View File

@ -57,10 +57,7 @@ void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state)
s->gpio_regs[gpio] = new_reg;
/* This is will work until we fix the binding between MacIO and
* the MPIC properly so we can route all GPIOs and avoid going
* via the top level platform code.
*
/*
* Note that we probably need to get access to the MPIC config to
* decode polarity since qemu always use "raise" regardless.
*
@ -152,25 +149,15 @@ static const MemoryRegionOps macio_gpio_ops = {
},
};
static void macio_gpio_realize(DeviceState *dev, Error **errp)
{
MacIOGPIOState *s = MACIO_GPIO(dev);
s->gpio_extirqs[1] = qdev_get_gpio_in(DEVICE(s->pic),
NEWWORLD_EXTING_GPIO1);
s->gpio_extirqs[9] = qdev_get_gpio_in(DEVICE(s->pic),
NEWWORLD_EXTING_GPIO9);
}
static void macio_gpio_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
MacIOGPIOState *s = MACIO_GPIO(obj);
int i;
object_property_add_link(obj, "pic", TYPE_OPENPIC,
(Object **) &s->pic,
qdev_prop_allow_set_link_before_realize,
0);
for (i = 0; i < 10; i++) {
sysbus_init_irq(sbd, &s->gpio_extirqs[i]);
}
memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj,
"gpio", 0x30);
@ -207,7 +194,6 @@ static void macio_gpio_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
dc->realize = macio_gpio_realize;
dc->reset = macio_gpio_reset;
dc->vmsd = &vmstate_macio_gpio;
nc->nmi_monitor_handler = macio_gpio_nmi;

53
hw/misc/macio/macio.c
View File

@ -140,7 +140,7 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
DeviceState *pic_dev = DEVICE(os->pic);
DeviceState *pic_dev = DEVICE(&os->pic);
Error *err = NULL;
SysBusDevice *sysbus_dev;
@ -150,6 +150,14 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
return;
}
/* Heathrow PIC */
if (!qdev_realize(DEVICE(&os->pic), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&os->pic);
memory_region_add_subregion(&s->bar, 0x0,
sysbus_mmio_get_region(sysbus_dev, 0));
qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
s->frequency);
if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
@ -175,11 +183,6 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
sysbus_mmio_get_region(sysbus_dev, 0));
pmac_format_nvram_partition(&os->nvram, os->nvram.size);
/* Heathrow PIC */
sysbus_dev = SYS_BUS_DEVICE(os->pic);
memory_region_add_subregion(&s->bar, 0x0,
sysbus_mmio_get_region(sysbus_dev, 0));
/* IDE buses */
macio_realize_ide(s, &os->ide[0],
qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
@ -218,10 +221,7 @@ static void macio_oldworld_init(Object *obj)
DeviceState *dev;
int i;
object_property_add_link(obj, "pic", TYPE_HEATHROW,
(Object **) &os->pic,
qdev_prop_allow_set_link_before_realize,
0);
object_initialize_child(OBJECT(s), "pic", &os->pic, TYPE_HEATHROW);
object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
@ -273,7 +273,7 @@ static void macio_newworld_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
DeviceState *pic_dev = DEVICE(ns->pic);
DeviceState *pic_dev = DEVICE(&ns->pic);
Error *err = NULL;
SysBusDevice *sysbus_dev;
MemoryRegion *timer_memory = NULL;
@ -284,17 +284,19 @@ static void macio_newworld_realize(PCIDevice *d, Error **errp)
return;
}
/* OpenPIC */
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
sysbus_dev = SYS_BUS_DEVICE(&ns->pic);
sysbus_realize_and_unref(sysbus_dev, &error_fatal);
memory_region_add_subregion(&s->bar, 0x40000,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_dev = SYS_BUS_DEVICE(&s->escc);
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
NEWWORLD_ESCCB_IRQ));
sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
NEWWORLD_ESCCA_IRQ));
/* OpenPIC */
sysbus_dev = SYS_BUS_DEVICE(ns->pic);
memory_region_add_subregion(&s->bar, 0x40000,
sysbus_mmio_get_region(sysbus_dev, 0));
/* IDE buses */
macio_realize_ide(s, &ns->ide[0],
qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_IRQ),
@ -322,14 +324,16 @@ static void macio_newworld_realize(PCIDevice *d, Error **errp)
if (ns->has_pmu) {
/* GPIOs */
sysbus_dev = SYS_BUS_DEVICE(&ns->gpio);
object_property_set_link(OBJECT(&ns->gpio), "pic", OBJECT(pic_dev),
&error_abort);
memory_region_add_subregion(&s->bar, 0x50,
sysbus_mmio_get_region(sysbus_dev, 0));
if (!qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&ns->gpio);
sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
NEWWORLD_EXTING_GPIO1));
sysbus_connect_irq(sysbus_dev, 9, qdev_get_gpio_in(pic_dev,
NEWWORLD_EXTING_GPIO9));
memory_region_add_subregion(&s->bar, 0x50,
sysbus_mmio_get_region(sysbus_dev, 0));
/* PMU */
object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU);
@ -369,10 +373,7 @@ static void macio_newworld_init(Object *obj)
NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
int i;
object_property_add_link(obj, "pic", TYPE_OPENPIC,
(Object **) &ns->pic,
qdev_prop_allow_set_link_before_realize,
0);
object_initialize_child(OBJECT(s), "pic", &ns->pic, TYPE_OPENPIC);
object_initialize_child(OBJECT(s), "gpio", &ns->gpio, TYPE_MACIO_GPIO);
@ -456,8 +457,6 @@ static void macio_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_OTHERS << 8;
device_class_set_props(dc, macio_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
/* Reason: requires PIC property links to be set in macio_*_realize() */
dc->user_creatable = false;
}
static const TypeInfo macio_bus_info = {

71
hw/ppc/mac_newworld.c
View File

@ -139,6 +139,7 @@ static void ppc_core99_init(MachineState *machine)
int machine_arch;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL;
hwaddr nvram_addr = 0xFFF04000;
uint64_t tbfreq;
unsigned int smp_cpus = machine->smp.cpus;
@ -292,18 +293,6 @@ static void ppc_core99_init(MachineState *machine)
}
}
pic_dev = qdev_new(TYPE_OPENPIC);
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
s = SYS_BUS_DEVICE(pic_dev);
sysbus_realize_and_unref(s, &error_fatal);
k = 0;
for (i = 0; i < smp_cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
}
}
g_free(openpic_irqs);
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
/* Uninorth AGP bus */
@ -320,35 +309,24 @@ static void ppc_core99_init(MachineState *machine)
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
machine_arch = ARCH_MAC99_U3;
} else {
/* Use values found on a real PowerMac */
/* Uninorth AGP bus */
dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
s = SYS_BUS_DEVICE(dev);
uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
s = SYS_BUS_DEVICE(uninorth_agp_dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
/* Uninorth internal bus */
dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
s = SYS_BUS_DEVICE(dev);
uninorth_internal_dev = qdev_new(
TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
s = SYS_BUS_DEVICE(uninorth_internal_dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, 0xf4800000);
sysbus_mmio_map(s, 1, 0xf4c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
/* Uninorth main bus */
dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
@ -364,10 +342,6 @@ static void ppc_core99_init(MachineState *machine)
sysbus_mmio_map(s, 0, 0xf2800000);
sysbus_mmio_map(s, 1, 0xf2c00000);
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
}
machine_arch = ARCH_MAC99;
}
@ -392,8 +366,6 @@ static void ppc_core99_init(MachineState *machine)
qdev_prop_set_uint64(dev, "frequency", tbfreq);
qdev_prop_set_bit(dev, "has-pmu", has_pmu);
qdev_prop_set_bit(dev, "has-adb", has_adb);
object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
&error_abort);
escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
@ -401,6 +373,37 @@ static void ppc_core99_init(MachineState *machine)
pci_realize_and_unref(macio, pci_bus, &error_fatal);
pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic"));
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(DEVICE(uninorth_pci), i,
qdev_get_gpio_in(pic_dev, 0x1b + i));
}
/* TODO: additional PCI buses only wired up for 32-bit machines */
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) {
/* Uninorth AGP bus */
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(uninorth_agp_dev, i,
qdev_get_gpio_in(pic_dev, 0x1b + i));
}
/* Uninorth internal bus */
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(uninorth_internal_dev, i,
qdev_get_gpio_in(pic_dev, 0x1b + i));
}
}
/* OpenPIC */
s = SYS_BUS_DEVICE(pic_dev);
k = 0;
for (i = 0; i < smp_cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
}
}
g_free(openpic_irqs);
/* We only emulate 2 out of 3 IDE controllers for now */
ide_drive_get(hd, ARRAY_SIZE(hd));

76
hw/ppc/mac_oldworld.c
View File

@ -98,7 +98,7 @@ static void ppc_heathrow_init(MachineState *machine)
MACIOIDEState *macio_ide;
ESCCState *escc;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
DeviceState *dev, *pic_dev, *grackle_dev;
BusState *adb_bus;
uint64_t bios_addr;
int bios_size;
@ -227,23 +227,6 @@ static void ppc_heathrow_init(MachineState *machine)
}
}
/* XXX: we register only 1 output pin for heathrow PIC */
pic_dev = qdev_new(TYPE_HEATHROW);
sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal);
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
qdev_connect_gpio_out(pic_dev, 0,
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
break;
default:
error_report("Bus model not supported on OldWorld Mac machine");
exit(1);
}
}
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
@ -251,16 +234,10 @@ static void ppc_heathrow_init(MachineState *machine)
tbfreq = TBFREQ;
}
/* init basic PC hardware */
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
error_report("Only 6xx bus is supported on heathrow machine");
exit(1);
}
/* Grackle PCI host bridge */
dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
s = SYS_BUS_DEVICE(dev);
grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000);
s = SYS_BUS_DEVICE(grackle_dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, GRACKLE_BASE);
@ -272,26 +249,12 @@ static void ppc_heathrow_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0xfe000000,
sysbus_mmio_get_region(s, 3));
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x15 + i));
}
pci_bus = PCI_HOST_BRIDGE(dev)->bus;
pci_vga_init(pci_bus);
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus;
/* MacIO */
macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
&error_abort);
escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
@ -299,6 +262,34 @@ static void ppc_heathrow_init(MachineState *machine)
pci_realize_and_unref(macio, pci_bus, &error_fatal);
pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic"));
for (i = 0; i < 4; i++) {
qdev_connect_gpio_out(grackle_dev, i,
qdev_get_gpio_in(pic_dev, 0x15 + i));
}
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
/* XXX: we register only 1 output pin for heathrow PIC */
qdev_connect_gpio_out(pic_dev, 0,
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
break;
default:
error_report("Bus model not supported on OldWorld Mac machine");
exit(1);
}
}
pci_vga_init(pci_bus);
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
}
/* MacIO IDE */
ide_drive_get(hd, ARRAY_SIZE(hd));
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
macio_ide_init_drives(macio_ide, hd);
@ -307,6 +298,7 @@ static void ppc_heathrow_init(MachineState *machine)
"ide[1]"));
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
/* MacIO CUDA/ADB */
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
dev = qdev_new(TYPE_ADB_KEYBOARD);

2
include/hw/misc/macio/gpio.h
View File

@ -38,8 +38,6 @@ struct MacIOGPIOState {
SysBusDevice parent;
/*< public >*/
OpenPICState *pic;
MemoryRegion gpiomem;
qemu_irq gpio_extirqs[10];
uint8_t gpio_levels[8];

4
include/hw/misc/macio/macio.h
View File

@ -99,7 +99,7 @@ struct OldWorldMacIOState {
MacIOState parent_obj;
/*< public >*/
HeathrowState *pic;
HeathrowState pic;
MacIONVRAMState nvram;
MACIOIDEState ide[2];
@ -115,7 +115,7 @@ struct NewWorldMacIOState {
bool has_pmu;
bool has_adb;
OpenPICState *pic;
OpenPICState pic;
MACIOIDEState ide[2];
MacIOGPIOState gpio;
};