accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced()
Forward tlb_flush_page_bits_by_mmuidx_all_cpus_synced to tlb_flush_range_by_mmuidx_all_cpus_synced passing TARGET_PAGE_SIZE. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210509151618.2331764-7-f4bug@amsat.org Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -887,16 +887,20 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
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idxmap, bits);
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idxmap, bits);
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}
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}
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void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
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void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
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target_ulong addr,
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target_ulong addr,
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target_ulong len,
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uint16_t idxmap,
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uint16_t idxmap,
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unsigned bits)
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unsigned bits)
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{
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{
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TLBFlushRangeData d, *p;
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TLBFlushRangeData d, *p;
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CPUState *dst_cpu;
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CPUState *dst_cpu;
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/* If all bits are significant, this devolves to tlb_flush_page. */
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/*
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if (bits >= TARGET_LONG_BITS) {
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* If all bits are significant, and len is small,
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* this devolves to tlb_flush_page.
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*/
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if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
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tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap);
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tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap);
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return;
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return;
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}
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}
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@ -908,7 +912,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
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/* This should already be page aligned */
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/* This should already be page aligned */
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d.addr = addr & TARGET_PAGE_MASK;
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d.addr = addr & TARGET_PAGE_MASK;
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d.len = TARGET_PAGE_SIZE;
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d.len = len;
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d.idxmap = idxmap;
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d.idxmap = idxmap;
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d.bits = bits;
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d.bits = bits;
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@ -926,6 +930,15 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
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RUN_ON_CPU_HOST_PTR(p));
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RUN_ON_CPU_HOST_PTR(p));
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}
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}
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void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
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target_ulong addr,
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uint16_t idxmap,
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unsigned bits)
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{
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tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu, addr, TARGET_PAGE_SIZE,
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idxmap, bits);
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}
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/* update the TLBs so that writes to code in the virtual page 'addr'
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/* update the TLBs so that writes to code in the virtual page 'addr'
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can be detected */
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can be detected */
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void tlb_protect_code(ram_addr_t ram_addr)
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void tlb_protect_code(ram_addr_t ram_addr)
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@ -281,6 +281,11 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
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void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
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void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
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target_ulong len, uint16_t idxmap,
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target_ulong len, uint16_t idxmap,
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unsigned bits);
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unsigned bits);
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void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
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target_ulong addr,
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target_ulong len,
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uint16_t idxmap,
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unsigned bits);
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/**
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/**
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* tlb_set_page_with_attrs:
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* tlb_set_page_with_attrs:
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@ -397,6 +402,13 @@ static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
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unsigned bits)
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unsigned bits)
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{
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{
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}
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}
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static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
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target_ulong addr,
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target_long len,
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uint16_t idxmap,
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unsigned bits)
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{
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}
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#endif
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#endif
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/**
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/**
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* probe_access:
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* probe_access:
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