target/arm: Fold regime_tcr() and regime_tcr_value() together
The only caller of regime_tcr() is now regime_tcr_value(); fold the two together, and use the shorter and more natural 'regime_tcr' name for the new function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220714132303.1287193-4-peter.maydell@linaro.org
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@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env)
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static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint64_t addr)
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{
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uint64_t tcr = regime_tcr_value(env, mmu_idx);
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uint64_t tcr = regime_tcr(env, mmu_idx);
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int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
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int select = extract64(addr, 55, 1);
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@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
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ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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ARMMMUIdx mmu_idx, bool data)
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{
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uint64_t tcr = regime_tcr_value(env, mmu_idx);
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uint64_t tcr = regime_tcr(env, mmu_idx);
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bool epd, hpd, using16k, using64k, tsz_oob, ds;
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int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
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ARMCPU *cpu = env_archcpu(env);
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@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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{
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CPUARMTBFlags flags = {};
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ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
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uint64_t tcr = regime_tcr_value(env, mmu_idx);
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uint64_t tcr = regime_tcr(env, mmu_idx);
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uint64_t sctlr;
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int tbii, tbid;
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@ -777,26 +777,20 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
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return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
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}
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/* Return the TCR controlling this translation regime */
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static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
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/* Return the value of the TCR controlling this translation regime */
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static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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if (mmu_idx == ARMMMUIdx_Stage2) {
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return &env->cp15.vtcr_el2;
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return env->cp15.vtcr_el2.raw_tcr;
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}
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if (mmu_idx == ARMMMUIdx_Stage2_S) {
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/*
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* Note: Secure stage 2 nominally shares fields from VTCR_EL2, but
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* those are not currently used by QEMU, so just return VSTCR_EL2.
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*/
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return &env->cp15.vstcr_el2;
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return env->cp15.vstcr_el2.raw_tcr;
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}
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return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
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}
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/* Return the raw value of the TCR controlling this translation regime */
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static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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return regime_tcr(env, mmu_idx)->raw_tcr;
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return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr;
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}
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/**
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@ -315,7 +315,7 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint32_t *table, uint32_t address)
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{
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/* Note that we can only get here for an AArch32 PL0/PL1 lookup */
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uint64_t tcr = regime_tcr_value(env, mmu_idx);
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uint64_t tcr = regime_tcr(env, mmu_idx);
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int maskshift = extract32(tcr, 0, 3);
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uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift);
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uint32_t base_mask;
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@ -824,7 +824,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
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static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
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ARMMMUIdx mmu_idx)
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{
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uint64_t tcr = regime_tcr_value(env, mmu_idx);
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uint64_t tcr = regime_tcr(env, mmu_idx);
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uint32_t el = regime_el(env, mmu_idx);
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int select, tsz;
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bool epd, hpd;
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@ -998,7 +998,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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uint32_t attrs;
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int32_t stride;
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int addrsize, inputsize, outputsize;
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uint64_t tcr = regime_tcr_value(env, mmu_idx);
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uint64_t tcr = regime_tcr(env, mmu_idx);
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int ap, ns, xn, pxn;
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uint32_t el = regime_el(env, mmu_idx);
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uint64_t descaddrmask;
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@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
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return true;
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}
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if (arm_feature(env, ARM_FEATURE_LPAE)
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&& (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) {
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&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
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return true;
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}
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return false;
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