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target/sparc: Move UDIV, SDIV to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-01 23:46:47 -07:00
parent 4ee85ea94b
commit c26368532d
3 changed files with 27 additions and 33 deletions
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4
target/sparc/helper.c
View File

@ -102,9 +102,7 @@ static target_ulong do_udiv(CPUSPARCState *env, target_ulong a,
}
if (cc) {
env->cc_dst = x0;
env->cc_src2 = overflow;
env->cc_op = CC_OP_DIV;
}
return x0;
}
@ -143,9 +141,7 @@ static target_ulong do_sdiv(CPUSPARCState *env, target_ulong a,
}
if (cc) {
env->cc_dst = x0;
env->cc_src2 = overflow;
env->cc_op = CC_OP_DIV;
}
return x0;
}

2
target/sparc/insns.decode
View File

@ -173,6 +173,8 @@ SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{

54
target/sparc/translate.c
View File

@ -710,6 +710,26 @@ static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
gen_helper_sdivx(dst, tcg_env, src1, src2);
}
static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_udiv(dst, tcg_env, src1, src2);
}
static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_sdiv(dst, tcg_env, src1, src2);
}
static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_udiv_cc(dst, tcg_env, src1, src2);
}
static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_sdiv_cc(dst, tcg_env, src1, src2);
}
// 1
static void gen_op_eval_ba(TCGv dst)
{
@ -2919,6 +2939,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
#ifdef TARGET_SPARC64
# define avail_32(C) false
# define avail_ASR17(C) false
# define avail_DIV(C) true
# define avail_MUL(C) true
# define avail_POWERDOWN(C) false
# define avail_64(C) true
@ -2927,6 +2948,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
#else
# define avail_32(C) true
# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
# define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV)
# define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
# define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN)
# define avail_64(C) false
@ -4136,6 +4158,8 @@ TRANS(SMUL, MUL, do_logic, a, gen_op_smul, NULL)
TRANS(UDIVX, 64, do_arith, a, -1, gen_op_udivx, NULL, NULL)
TRANS(SDIVX, 64, do_arith, a, -1, gen_op_sdivx, NULL, NULL)
TRANS(UDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_udiv, NULL, gen_op_udivcc)
TRANS(SDIV, DIV, do_arith, a, CC_OP_DIV, gen_op_sdiv, NULL, gen_op_sdivcc)
static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
{
@ -4623,35 +4647,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
#endif
} else if (xop < 0x36) {
if (xop < 0x20) {
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
case 0xe: /* udiv */
CHECK_IU_FEATURE(dc, DIV);
if (xop & 0x10) {
gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
dc->cc_op = CC_OP_DIV;
} else {
gen_helper_udiv(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
}
break;
case 0xf: /* sdiv */
CHECK_IU_FEATURE(dc, DIV);
if (xop & 0x10) {
gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
dc->cc_op = CC_OP_DIV;
} else {
gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1,
cpu_src2);
}
break;
default:
goto illegal_insn;
}
gen_store_gpr(dc, rd, cpu_dst);
goto illegal_insn;
} else {
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);