target/ppc: Implemented xvf*ger*
Implement the following PowerISA v3.1 instructions: xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update) xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate xvf64ger: VSX Vector 64-bit Floating-Point GER (rank-1 update) xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220524140537.27451-5-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Lucas Mateus Castro (alqotel)
Daniel Henrique Barboza
parent
6d525ca972
commit
c29018cc73
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@ -2643,6 +2643,8 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
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#define VsrSW(i) s32[i]
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#define VsrD(i) u64[i]
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#define VsrSD(i) s64[i]
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#define VsrSF(i) f32[i]
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#define VsrDF(i) f64[i]
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#else
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#define VsrB(i) u8[15 - (i)]
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#define VsrSB(i) s8[15 - (i)]
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@ -2652,6 +2654,8 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
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#define VsrSW(i) s32[3 - (i)]
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#define VsrD(i) u64[1 - (i)]
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#define VsrSD(i) s64[1 - (i)]
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#define VsrSF(i) f32[3 - (i)]
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#define VsrDF(i) f64[1 - (i)]
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#endif
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static inline int vsr64_offset(int i, bool high)
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@ -414,7 +414,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles)
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ppc_store_fpscr(env, val);
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}
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void helper_fpscr_check_status(CPUPPCState *env)
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static void do_fpscr_check_status(CPUPPCState *env, uintptr_t raddr)
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{
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CPUState *cs = env_cpu(env);
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target_ulong fpscr = env->fpscr;
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@ -455,13 +455,19 @@ void helper_fpscr_check_status(CPUPPCState *env)
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}
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cs->exception_index = POWERPC_EXCP_PROGRAM;
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env->error_code = error | POWERPC_EXCP_FP;
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env->fpscr |= error ? FP_FEX : 0;
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/* Deferred floating-point exception after target FPSCR update */
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if (fp_exceptions_enabled(env)) {
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raise_exception_err_ra(env, cs->exception_index,
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env->error_code, GETPC());
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env->error_code, raddr);
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}
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}
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void helper_fpscr_check_status(CPUPPCState *env)
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{
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do_fpscr_check_status(env, GETPC());
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}
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static void do_float_check_status(CPUPPCState *env, bool change_fi,
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uintptr_t raddr)
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{
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@ -3468,3 +3474,187 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
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*xt = t;
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do_float_check_status(env, true, GETPC());
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}
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static inline void vsxger_excp(CPUPPCState *env, uintptr_t retaddr)
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{
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/*
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* XV*GER instructions execute and set the FPSCR as if exceptions
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* are disabled and only at the end throw an exception
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*/
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target_ulong enable;
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enable = env->fpscr & (FP_ENABLES | FP_FI | FP_FR);
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env->fpscr &= ~(FP_ENABLES | FP_FI | FP_FR);
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int status = get_float_exception_flags(&env->fp_status);
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if (unlikely(status & float_flag_invalid)) {
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if (status & float_flag_invalid_snan) {
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float_invalid_op_vxsnan(env, 0);
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}
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if (status & float_flag_invalid_imz) {
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float_invalid_op_vximz(env, false, 0);
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}
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if (status & float_flag_invalid_isi) {
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float_invalid_op_vxisi(env, false, 0);
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}
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}
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do_float_check_status(env, false, retaddr);
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env->fpscr |= enable;
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do_fpscr_check_status(env, retaddr);
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}
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typedef void vsxger_zero(ppc_vsr_t *at, int, int);
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typedef void vsxger_muladd_f(ppc_vsr_t *, ppc_vsr_t *, ppc_vsr_t *, int, int,
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int flags, float_status *s);
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static void vsxger_muladd32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
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int j, int flags, float_status *s)
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{
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at[i].VsrSF(j) = float32_muladd(a->VsrSF(i), b->VsrSF(j),
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at[i].VsrSF(j), flags, s);
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}
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static void vsxger_mul32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
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int j, int flags, float_status *s)
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{
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at[i].VsrSF(j) = float32_mul(a->VsrSF(i), b->VsrSF(j), s);
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}
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static void vsxger_zero32(ppc_vsr_t *at, int i, int j)
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{
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at[i].VsrSF(j) = float32_zero;
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}
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static void vsxger_muladd64(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
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int j, int flags, float_status *s)
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{
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if (j >= 2) {
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j -= 2;
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at[i].VsrDF(j) = float64_muladd(a[i / 2].VsrDF(i % 2), b->VsrDF(j),
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at[i].VsrDF(j), flags, s);
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}
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}
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static void vsxger_mul64(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
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int j, int flags, float_status *s)
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{
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if (j >= 2) {
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j -= 2;
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at[i].VsrDF(j) = float64_mul(a[i / 2].VsrDF(i % 2), b->VsrDF(j), s);
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}
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}
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static void vsxger_zero64(ppc_vsr_t *at, int i, int j)
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{
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if (j >= 2) {
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j -= 2;
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at[i].VsrDF(j) = float64_zero;
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}
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}
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static void vsxger(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask, bool acc, bool neg_mul,
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bool neg_acc, vsxger_muladd_f mul, vsxger_muladd_f muladd,
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vsxger_zero zero)
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{
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int i, j, xmsk_bit, ymsk_bit, op_flags;
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uint8_t xmsk = mask & 0x0F;
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uint8_t ymsk = (mask >> 4) & 0x0F;
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float_status *excp_ptr = &env->fp_status;
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op_flags = (neg_acc ^ neg_mul) ? float_muladd_negate_c : 0;
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op_flags |= (neg_mul) ? float_muladd_negate_result : 0;
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helper_reset_fpstatus(env);
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for (i = 0, xmsk_bit = 1 << 3; i < 4; i++, xmsk_bit >>= 1) {
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for (j = 0, ymsk_bit = 1 << 3; j < 4; j++, ymsk_bit >>= 1) {
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if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) {
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if (acc) {
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muladd(at, a, b, i, j, op_flags, excp_ptr);
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} else {
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mul(at, a, b, i, j, op_flags, excp_ptr);
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}
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} else {
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zero(at, i, j);
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}
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}
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}
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vsxger_excp(env, GETPC());
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}
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QEMU_FLATTEN
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void helper_XVF32GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, false, false, false, vsxger_mul32,
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vsxger_muladd32, vsxger_zero32);
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}
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QEMU_FLATTEN
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void helper_XVF32GERPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, false, false, vsxger_mul32,
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vsxger_muladd32, vsxger_zero32);
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}
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QEMU_FLATTEN
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void helper_XVF32GERPN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, false, true, vsxger_mul32,
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vsxger_muladd32, vsxger_zero32);
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}
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QEMU_FLATTEN
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void helper_XVF32GERNP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, true, false, vsxger_mul32,
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vsxger_muladd32, vsxger_zero32);
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}
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QEMU_FLATTEN
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void helper_XVF32GERNN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, true, true, vsxger_mul32,
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vsxger_muladd32, vsxger_zero32);
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}
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QEMU_FLATTEN
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void helper_XVF64GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, false, false, false, vsxger_mul64,
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vsxger_muladd64, vsxger_zero64);
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}
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QEMU_FLATTEN
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void helper_XVF64GERPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, false, false, vsxger_mul64,
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vsxger_muladd64, vsxger_zero64);
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}
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QEMU_FLATTEN
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void helper_XVF64GERPN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, false, true, vsxger_mul64,
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vsxger_muladd64, vsxger_zero64);
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}
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QEMU_FLATTEN
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void helper_XVF64GERNP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, true, false, vsxger_mul64,
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vsxger_muladd64, vsxger_zero64);
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}
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QEMU_FLATTEN
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void helper_XVF64GERNN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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vsxger(env, a, b, at, mask, true, true, true, vsxger_mul64,
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vsxger_muladd64, vsxger_zero64);
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}
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@ -550,6 +550,16 @@ DEF_HELPER_5(XVI16GER2, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF32GER, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF32GERPP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF32GERPN, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF32GERNP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF32GERNN, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF64GER, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF64GERPP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF64GERPN, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF64GERNP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVF64GERNN, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_2(efscfsi, i32, env, i32)
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DEF_HELPER_2(efscfui, i32, env, i32)
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@ -178,6 +178,7 @@
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# 32 bit GER instructions have all mask bits considered 1
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&MMIRR_XX3 xa xb xt pmsk xmsk ymsk
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%xx_at 23:3
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%xx_xa_pair 2:1 17:4 !function=times_2
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@XX3_at ...... ... .. ..... ..... ........ ... &MMIRR_XX3 xt=%xx_at xb=%xx_xb \
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pmsk=255 xmsk=15 ymsk=15
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@ -761,3 +762,15 @@ XVI16GER2PP 111011 ... -- ..... ..... 01101011 ..- @XX3_at xa=%xx_xa
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XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..- @XX3_at xa=%xx_xa
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XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=%xx_xa
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XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=%xx_xa
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XVF32GER 111011 ... -- ..... ..... 00011011 ..- @XX3_at xa=%xx_xa
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XVF32GERPP 111011 ... -- ..... ..... 00011010 ..- @XX3_at xa=%xx_xa
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XVF32GERPN 111011 ... -- ..... ..... 10011010 ..- @XX3_at xa=%xx_xa
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XVF32GERNP 111011 ... -- ..... ..... 01011010 ..- @XX3_at xa=%xx_xa
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XVF32GERNN 111011 ... -- ..... ..... 11011010 ..- @XX3_at xa=%xx_xa
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XVF64GER 111011 ... -- .... 0 ..... 00111011 ..- @XX3_at xa=%xx_xa_pair
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XVF64GERPP 111011 ... -- .... 0 ..... 00111010 ..- @XX3_at xa=%xx_xa_pair
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XVF64GERPN 111011 ... -- .... 0 ..... 10111010 ..- @XX3_at xa=%xx_xa_pair
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XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=%xx_xa_pair
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XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
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@ -2898,6 +2898,18 @@ TRANS64(PMXVI16GER2PP, do_ger, gen_helper_XVI16GER2PP)
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TRANS64(PMXVI16GER2S, do_ger, gen_helper_XVI16GER2S)
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TRANS64(PMXVI16GER2SPP, do_ger, gen_helper_XVI16GER2SPP)
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TRANS(XVF32GER, do_ger, gen_helper_XVF32GER)
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TRANS(XVF32GERPP, do_ger, gen_helper_XVF32GERPP)
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TRANS(XVF32GERPN, do_ger, gen_helper_XVF32GERPN)
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TRANS(XVF32GERNP, do_ger, gen_helper_XVF32GERNP)
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TRANS(XVF32GERNN, do_ger, gen_helper_XVF32GERNN)
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TRANS(XVF64GER, do_ger, gen_helper_XVF64GER)
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TRANS(XVF64GERPP, do_ger, gen_helper_XVF64GERPP)
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TRANS(XVF64GERPN, do_ger, gen_helper_XVF64GERPN)
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TRANS(XVF64GERNP, do_ger, gen_helper_XVF64GERNP)
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TRANS(XVF64GERNN, do_ger, gen_helper_XVF64GERNN)
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#undef GEN_XX2FORM
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#undef GEN_XX3FORM
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#undef GEN_XX2IFORM
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