target/mips: Avoid tcg_const_* throughout
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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0bcc6b4cfd
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c29e79af27
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@ -704,8 +704,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
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gen_base_offset_addr(ctx, t0, base, offset);
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t1 = tcg_const_tl(reglist);
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t2 = tcg_const_i32(ctx->mem_idx);
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t1 = tcg_constant_tl(reglist);
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t2 = tcg_constant_i32(ctx->mem_idx);
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save_cpu_state(ctx, 1);
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switch (opc) {
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@ -1072,7 +1072,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
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uint32_t XRx = XRb ? XRb : XRc;
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/* ...and do half-word-wise max/min with one operand 0 */
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TCGv_i32 t0 = tcg_temp_new();
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TCGv_i32 t1 = tcg_const_i32(0);
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TCGv_i32 t1 = tcg_constant_i32(0);
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/* the left half-word first */
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tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
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@ -1163,7 +1163,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
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uint32_t XRx = XRb ? XRb : XRc;
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/* ...and do byte-wise max/min with one operand 0 */
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TCGv_i32 t0 = tcg_temp_new();
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TCGv_i32 t1 = tcg_const_i32(0);
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TCGv_i32 t1 = tcg_constant_i32(0);
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int32_t i;
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/* the leftmost byte (byte 3) first */
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@ -3359,7 +3359,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
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case 0:
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/* PRECR_SRA_PH_W */
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{
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TCGv_i32 sa_t = tcg_const_i32(rd);
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TCGv_i32 sa_t = tcg_constant_i32(rd);
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gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
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cpu_gpr[rt]);
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gen_store_gpr(v1_t, rt);
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@ -3368,7 +3368,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
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case 1:
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/* PRECR_SRA_R_PH_W */
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{
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TCGv_i32 sa_t = tcg_const_i32(rd);
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TCGv_i32 sa_t = tcg_constant_i32(rd);
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gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
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cpu_gpr[rt]);
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gen_store_gpr(v1_t, rt);
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@ -3864,10 +3864,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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check_nms(ctx);
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if (rt != 0) {
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TCGv t0 = tcg_temp_new();
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TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));
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TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)
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<< 1);
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TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1));
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TCGv_i32 shift =
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tcg_constant_i32(extract32(ctx->opcode, 0, 5));
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TCGv_i32 shiftx =
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tcg_constant_i32(extract32(ctx->opcode, 7, 4) << 1);
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TCGv_i32 stripe =
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tcg_constant_i32(extract32(ctx->opcode, 6, 1));
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gen_load_gpr(t0, rs);
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gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
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@ -4500,7 +4502,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
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/* make sure instructions are on a halfword boundary */
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if (ctx->base.pc_next & 0x1) {
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TCGv tmp = tcg_const_tl(ctx->base.pc_next);
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TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
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generate_exception_end(ctx, EXCP_AdEL);
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return 2;
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@ -2099,14 +2099,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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gen_store_gpr(t1, rt);
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break;
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case OPC_LDPC:
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t1 = tcg_const_tl(pc_relative_pc(ctx));
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t1 = tcg_constant_tl(pc_relative_pc(ctx));
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gen_op_addr_add(ctx, t0, t0, t1);
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tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
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gen_store_gpr(t0, rt);
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break;
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#endif
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case OPC_LWPC:
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t1 = tcg_const_tl(pc_relative_pc(ctx));
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t1 = tcg_constant_tl(pc_relative_pc(ctx));
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gen_op_addr_add(ctx, t0, t0, t1);
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tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
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gen_store_gpr(t0, rt);
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@ -2733,7 +2733,7 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc,
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t0 = tcg_temp_new();
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gen_load_gpr(t0, rt);
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t1 = tcg_const_tl(0);
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t1 = tcg_constant_tl(0);
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t2 = tcg_temp_new();
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gen_load_gpr(t2, rs);
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switch (opc) {
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@ -3084,8 +3084,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
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break;
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case R6_OPC_DIVU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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TCGv t2 = tcg_constant_tl(0);
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TCGv t3 = tcg_constant_tl(1);
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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@ -3095,8 +3095,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
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break;
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case R6_OPC_MODU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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TCGv t2 = tcg_constant_tl(0);
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TCGv t3 = tcg_constant_tl(1);
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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@ -3175,16 +3175,16 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
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break;
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case R6_OPC_DDIVU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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TCGv t2 = tcg_constant_tl(0);
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TCGv t3 = tcg_constant_tl(1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
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}
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break;
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case R6_OPC_DMODU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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TCGv t2 = tcg_constant_tl(0);
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TCGv t3 = tcg_constant_tl(1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
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}
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@ -3248,8 +3248,8 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
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break;
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case MMI_OPC_DIVU1:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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TCGv t2 = tcg_constant_tl(0);
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TCGv t3 = tcg_constant_tl(1);
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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@ -3304,8 +3304,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
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break;
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case OPC_DIVU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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TCGv t2 = tcg_constant_tl(0);
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TCGv t3 = tcg_constant_tl(1);
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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@ -3355,8 +3355,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
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break;
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case OPC_DDIVU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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TCGv t2 = tcg_constant_tl(0);
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TCGv t3 = tcg_constant_tl(1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
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tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
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@ -4916,7 +4916,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
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case OPC_WSBH:
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{
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_const_tl(0x00FF00FF);
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TCGv t2 = tcg_constant_tl(0x00FF00FF);
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tcg_gen_shri_tl(t1, t0, 8);
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tcg_gen_and_tl(t1, t1, t2);
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@ -4936,7 +4936,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
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case OPC_DSBH:
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{
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
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TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL);
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tcg_gen_shri_tl(t1, t0, 8);
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tcg_gen_and_tl(t1, t1, t2);
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@ -4948,7 +4948,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
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case OPC_DSHD:
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{
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
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TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL);
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tcg_gen_shri_tl(t1, t0, 16);
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tcg_gen_and_tl(t1, t1, t2);
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@ -8459,7 +8459,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
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case 5:
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case 6:
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case 7:
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gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
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gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel));
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break;
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default:
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goto die;
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@ -9485,7 +9485,7 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
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static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
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int fs)
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{
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TCGv_i32 t1 = tcg_const_i32(0);
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TCGv_i32 t1 = tcg_constant_i32(0);
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TCGv_i32 fp0 = tcg_temp_new_i32();
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TCGv_i32 fp1 = tcg_temp_new_i32();
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TCGv_i32 fp2 = tcg_temp_new_i32();
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@ -9518,7 +9518,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
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static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
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int fs)
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{
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TCGv_i64 t1 = tcg_const_i64(0);
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TCGv_i64 t1 = tcg_constant_i64(0);
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TCGv_i64 fp0 = tcg_temp_new_i64();
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TCGv_i64 fp1 = tcg_temp_new_i64();
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TCGv_i64 fp2 = tcg_temp_new_i64();
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@ -11516,7 +11516,7 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
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static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
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int16_t offset)
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{
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TCGv_i32 t0 = tcg_const_i32(op);
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TCGv_i32 t0 = tcg_constant_i32(op);
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TCGv t1 = tcg_temp_new();
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gen_base_offset_addr(ctx, t1, base, offset);
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gen_helper_cache(cpu_env, t1, t0);
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@ -11860,7 +11860,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
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case OPC_PRECR_SRA_PH_W:
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check_dsp_r2(ctx);
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{
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TCGv_i32 sa_t = tcg_const_i32(v2);
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TCGv_i32 sa_t = tcg_constant_i32(v2);
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gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
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cpu_gpr[ret]);
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break;
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@ -11868,7 +11868,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
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case OPC_PRECR_SRA_R_PH_W:
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check_dsp_r2(ctx);
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{
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TCGv_i32 sa_t = tcg_const_i32(v2);
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TCGv_i32 sa_t = tcg_constant_i32(v2);
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gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
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cpu_gpr[ret]);
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break;
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@ -12057,14 +12057,14 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
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case OPC_PRECR_SRA_QH_PW:
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check_dsp_r2(ctx);
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{
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TCGv_i32 ret_t = tcg_const_i32(ret);
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TCGv_i32 ret_t = tcg_constant_i32(ret);
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gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
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break;
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}
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case OPC_PRECR_SRA_R_QH_PW:
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check_dsp_r2(ctx);
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{
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TCGv_i32 sa_v = tcg_const_i32(ret);
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TCGv_i32 sa_v = tcg_constant_i32(ret);
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gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
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break;
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}
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@ -243,8 +243,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
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return true;
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}
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c0 = tcg_const_tl(0);
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c1 = tcg_const_tl(0xffffffff);
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c0 = tcg_constant_tl(0);
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c1 = tcg_constant_tl(0xffffffff);
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ax = tcg_temp_new_i64();
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bx = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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