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target/mips: Avoid tcg_const_* throughout

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All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-25 17:46:54 -10:00
parent 0bcc6b4cfd
commit c29e79af27
5 changed files with 43 additions and 41 deletions
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4
target/mips/tcg/micromips_translate.c.inc
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@ -704,8 +704,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
gen_base_offset_addr(ctx, t0, base, offset);
t1 = tcg_const_tl(reglist);
t2 = tcg_const_i32(ctx->mem_idx);
t1 = tcg_constant_tl(reglist);
t2 = tcg_constant_i32(ctx->mem_idx);
save_cpu_state(ctx, 1);
switch (opc) {

4
target/mips/tcg/mxu_translate.c
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@ -1072,7 +1072,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do half-word-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_const_i32(0);
TCGv_i32 t1 = tcg_constant_i32(0);
/* the left half-word first */
tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
@ -1163,7 +1163,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do byte-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_const_i32(0);
TCGv_i32 t1 = tcg_constant_i32(0);
int32_t i;
/* the leftmost byte (byte 3) first */

16
target/mips/tcg/nanomips_translate.c.inc
View File

@ -3359,7 +3359,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case 0:
/* PRECR_SRA_PH_W */
{
TCGv_i32 sa_t = tcg_const_i32(rd);
TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
@ -3368,7 +3368,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case 1:
/* PRECR_SRA_R_PH_W */
{
TCGv_i32 sa_t = tcg_const_i32(rd);
TCGv_i32 sa_t = tcg_constant_i32(rd);
gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
cpu_gpr[rt]);
gen_store_gpr(v1_t, rt);
@ -3864,10 +3864,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_nms(ctx);
if (rt != 0) {
TCGv t0 = tcg_temp_new();
TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5));
TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4)
<< 1);
TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1));
TCGv_i32 shift =
tcg_constant_i32(extract32(ctx->opcode, 0, 5));
TCGv_i32 shiftx =
tcg_constant_i32(extract32(ctx->opcode, 7, 4) << 1);
TCGv_i32 stripe =
tcg_constant_i32(extract32(ctx->opcode, 6, 1));
gen_load_gpr(t0, rs);
gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
@ -4500,7 +4502,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
/* make sure instructions are on a halfword boundary */
if (ctx->base.pc_next & 0x1) {
TCGv tmp = tcg_const_tl(ctx->base.pc_next);
TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
generate_exception_end(ctx, EXCP_AdEL);
return 2;

56
target/mips/tcg/translate.c
View File

@ -2099,14 +2099,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_const_tl(pc_relative_pc(ctx));
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
t1 = tcg_const_tl(pc_relative_pc(ctx));
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
gen_store_gpr(t0, rt);
@ -2733,7 +2733,7 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc,
t0 = tcg_temp_new();
gen_load_gpr(t0, rt);
t1 = tcg_const_tl(0);
t1 = tcg_constant_tl(0);
t2 = tcg_temp_new();
gen_load_gpr(t2, rs);
switch (opc) {
@ -3084,8 +3084,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_DIVU:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
TCGv t2 = tcg_constant_tl(0);
TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@ -3095,8 +3095,8 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_MODU:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
TCGv t2 = tcg_constant_tl(0);
TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@ -3175,16 +3175,16 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
break;
case R6_OPC_DDIVU:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
TCGv t2 = tcg_constant_tl(0);
TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
}
break;
case R6_OPC_DMODU:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
TCGv t2 = tcg_constant_tl(0);
TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
}
@ -3248,8 +3248,8 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
break;
case MMI_OPC_DIVU1:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
TCGv t2 = tcg_constant_tl(0);
TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@ -3304,8 +3304,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
case OPC_DIVU:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
TCGv t2 = tcg_constant_tl(0);
TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
@ -3355,8 +3355,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
case OPC_DDIVU:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
TCGv t2 = tcg_constant_tl(0);
TCGv t3 = tcg_constant_tl(1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
@ -4916,7 +4916,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_WSBH:
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_const_tl(0x00FF00FF);
TCGv t2 = tcg_constant_tl(0x00FF00FF);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_and_tl(t1, t1, t2);
@ -4936,7 +4936,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSBH:
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_and_tl(t1, t1, t2);
@ -4948,7 +4948,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSHD:
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL);
tcg_gen_shri_tl(t1, t0, 16);
tcg_gen_and_tl(t1, t1, t2);
@ -8459,7 +8459,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 5:
case 6:
case 7:
gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel));
break;
default:
goto die;
@ -9485,7 +9485,7 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
int fs)
{
TCGv_i32 t1 = tcg_const_i32(0);
TCGv_i32 t1 = tcg_constant_i32(0);
TCGv_i32 fp0 = tcg_temp_new_i32();
TCGv_i32 fp1 = tcg_temp_new_i32();
TCGv_i32 fp2 = tcg_temp_new_i32();
@ -9518,7 +9518,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
int fs)
{
TCGv_i64 t1 = tcg_const_i64(0);
TCGv_i64 t1 = tcg_constant_i64(0);
TCGv_i64 fp0 = tcg_temp_new_i64();
TCGv_i64 fp1 = tcg_temp_new_i64();
TCGv_i64 fp2 = tcg_temp_new_i64();
@ -11516,7 +11516,7 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
int16_t offset)
{
TCGv_i32 t0 = tcg_const_i32(op);
TCGv_i32 t0 = tcg_constant_i32(op);
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
gen_helper_cache(cpu_env, t1, t0);
@ -11860,7 +11860,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_PH_W:
check_dsp_r2(ctx);
{
TCGv_i32 sa_t = tcg_const_i32(v2);
TCGv_i32 sa_t = tcg_constant_i32(v2);
gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
break;
@ -11868,7 +11868,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_R_PH_W:
check_dsp_r2(ctx);
{
TCGv_i32 sa_t = tcg_const_i32(v2);
TCGv_i32 sa_t = tcg_constant_i32(v2);
gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
cpu_gpr[ret]);
break;
@ -12057,14 +12057,14 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_PRECR_SRA_QH_PW:
check_dsp_r2(ctx);
{
TCGv_i32 ret_t = tcg_const_i32(ret);
TCGv_i32 ret_t = tcg_constant_i32(ret);
gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
break;
}
case OPC_PRECR_SRA_R_QH_PW:
check_dsp_r2(ctx);
{
TCGv_i32 sa_v = tcg_const_i32(ret);
TCGv_i32 sa_v = tcg_constant_i32(ret);
gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
break;
}

4
target/mips/tcg/tx79_translate.c
View File

@ -243,8 +243,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
return true;
}
c0 = tcg_const_tl(0);
c1 = tcg_const_tl(0xffffffff);
c0 = tcg_constant_tl(0);
c1 = tcg_constant_tl(0xffffffff);
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();