From c2bb8e1bcccb9d8228bc2ec55bbcbdb8f1ce774c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 9 Feb 2024 08:57:50 +0100 Subject: [PATCH] target/mips: Remove CPUMIPSState::saarp field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This field is never set, so remove the unreachable code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240209090513.9401-5-philmd@linaro.org> --- hw/misc/mips_itu.c | 6 ------ target/mips/cpu.h | 1 - 2 files changed, 7 deletions(-) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index db1220f8e0..d259a88d22 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -516,7 +516,6 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s = MIPS_ITU(dev); - CPUMIPSState *env; if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -533,11 +532,6 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) return; } - env = &MIPS_CPU(s->cpu0)->env; - if (env->saarp) { - s->saar = env->CP0_SAAR; - } - s->cell = g_new(ITCStorageCell, get_num_cells(s)); } diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d54e9a4a1c..ef1d9f279c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1174,7 +1174,6 @@ typedef struct CPUArchState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ - int saarp; /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields;