gt64xxx: qdev conversion
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno
parent
cf154394bd
commit
c2dd2a2352
119
hw/gt64xxx.c
119
hw/gt64xxx.c
@ -223,16 +223,14 @@
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#define GT_PCI0_HICMASK (0xca4 >> 2)
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#define GT_PCI1_SERR1MASK (0xca8 >> 2)
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typedef PCIHostState GT64120PCIState;
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#define PCI_MAPPING_ENTRY(regname) \
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target_phys_addr_t regname ##_start; \
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target_phys_addr_t regname ##_length; \
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int regname ##_handle
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typedef struct GT64120State {
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GT64120PCIState *pci;
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SysBusDevice busdev;
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PCIHostState pci;
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uint32_t regs[GT_REGS];
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PCI_MAPPING_ENTRY(PCI0IO);
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PCI_MAPPING_ENTRY(ISD);
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@ -525,13 +523,13 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
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/* not implemented */
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break;
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case GT_PCI0_CFGADDR:
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s->pci->config_reg = val & 0x80fffffc;
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s->pci.config_reg = val & 0x80fffffc;
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break;
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case GT_PCI0_CFGDATA:
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if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800))
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if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
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val = bswap32(val);
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if (s->pci->config_reg & (1u << 31))
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pci_data_write(s->pci->bus, s->pci->config_reg, val, 4);
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if (s->pci.config_reg & (1u << 31))
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pci_data_write(s->pci.bus, s->pci.config_reg, val, 4);
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break;
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/* Interrupts */
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@ -765,14 +763,14 @@ static uint32_t gt64120_readl (void *opaque,
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/* PCI Internal */
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case GT_PCI0_CFGADDR:
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val = s->pci->config_reg;
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val = s->pci.config_reg;
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break;
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case GT_PCI0_CFGDATA:
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if (!(s->pci->config_reg & (1 << 31)))
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if (!(s->pci.config_reg & (1 << 31)))
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val = 0xffffffff;
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else
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val = pci_data_read(s->pci->bus, s->pci->config_reg, 4);
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if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800))
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val = pci_data_read(s->pci.bus, s->pci.config_reg, 4);
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if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
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val = bswap32(val);
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break;
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@ -864,7 +862,7 @@ static CPUReadMemoryFunc * const gt64120_read[] = {
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>64120_readl,
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};
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static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
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static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int slot;
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@ -891,7 +889,7 @@ static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
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static int pci_irq_levels[4];
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static void pci_gt64120_set_irq(void *opaque, int irq_num, int level)
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static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
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{
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int i, pic_irq, pic_level;
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qemu_irq *pic = opaque;
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@ -1101,50 +1099,71 @@ static int gt64120_load(QEMUFile* f, void *opaque, int version_id)
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return 0;
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}
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PCIBus *pci_gt64120_init(qemu_irq *pic)
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PCIBus *gt64120_register(qemu_irq *pic)
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{
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SysBusDevice *s;
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GT64120State *d;
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DeviceState *dev;
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dev = qdev_create(NULL, "gt64120");
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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d = FROM_SYSBUS(GT64120State, s);
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d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
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gt64120_pci_set_irq, gt64120_pci_map_irq,
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pic, PCI_DEVFN(18, 0), 4);
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d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
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DEVICE_NATIVE_ENDIAN);
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pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
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return d->pci.bus;
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}
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static int gt64120_init(SysBusDevice *dev)
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{
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GT64120State *s;
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PCIDevice *d;
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s = qemu_mallocz(sizeof(GT64120State));
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s->pci = qemu_mallocz(sizeof(GT64120PCIState));
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s = FROM_SYSBUS(GT64120State, dev);
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s->pci->bus = pci_register_bus(NULL, "pci",
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pci_gt64120_set_irq, pci_gt64120_map_irq,
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pic, PCI_DEVFN(18, 0), 4);
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s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s,
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DEVICE_NATIVE_ENDIAN);
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d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
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0, NULL, NULL);
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qemu_register_reset(gt64120_reset, s);
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register_savevm(&dev->qdev, "GT64120 PCI Bus", 0, 1,
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gt64120_save, gt64120_load, &s->pci);
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return 0;
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}
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static int gt64120_pci_init(PCIDevice *d)
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{
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/* FIXME: Malta specific hw assumptions ahead */
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MARVELL);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_MARVELL_GT6412X);
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d->config[0x04] = 0x00;
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d->config[0x05] = 0x00;
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d->config[0x06] = 0x80;
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d->config[0x07] = 0x02;
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d->config[0x08] = 0x10;
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d->config[0x09] = 0x00;
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pci_set_word(d->config + PCI_COMMAND, 0);
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pci_set_word(d->config + PCI_STATUS,
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_byte(d->config + PCI_CLASS_REVISION, 0x10);
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pci_config_set_prog_interface(d->config, 0);
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
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pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
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pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
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pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
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pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
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pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
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pci_set_byte(d->config + 0x3d, 0x01);
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d->config[0x10] = 0x08;
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d->config[0x14] = 0x08;
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d->config[0x17] = 0x01;
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d->config[0x1B] = 0x1c;
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d->config[0x1F] = 0x1f;
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d->config[0x23] = 0x14;
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d->config[0x24] = 0x01;
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d->config[0x27] = 0x14;
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d->config[0x3D] = 0x01;
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gt64120_reset(s);
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register_savevm(&d->qdev, "GT64120 PCI Bus", 0, 1,
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gt64120_save, gt64120_load, d);
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return s->pci->bus;
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return 0;
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}
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static PCIDeviceInfo gt64120_pci_info = {
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.qdev.name = "gt64120_pci",
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.qdev.size = sizeof(PCIDevice),
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.init = gt64120_pci_init,
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};
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static void gt64120_pci_register_devices(void)
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{
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sysbus_register_dev("gt64120", sizeof(GT64120State),
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gt64120_init);
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pci_qdev_register(>64120_pci_info);
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}
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device_init(gt64120_pci_register_devices)
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@ -3,7 +3,7 @@
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/* Definitions for mips board emulation. */
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/* gt64xxx.c */
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PCIBus *pci_gt64120_init(qemu_irq *pic);
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PCIBus *gt64120_register(qemu_irq *pic);
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/* bonito.c */
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PCIBus *bonito_init(qemu_irq *pic);
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@ -921,7 +921,7 @@ void mips_malta_init (ram_addr_t ram_size,
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i8259 = i8259_init(env->irq[2]);
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/* Northbridge */
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pci_bus = pci_gt64120_init(i8259);
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pci_bus = gt64120_register(i8259);
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/* Southbridge */
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