xtensa: avoid "naked" qemu_log
Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
b81b971c7a
commit
c30f0d182f
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@ -63,8 +63,8 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
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default:
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qemu_log("%s from reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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return 0;
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}
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}
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@ -117,8 +117,8 @@ int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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break;
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default:
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qemu_log("%s to reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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return 0;
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}
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@ -254,8 +254,8 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
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env->config->exception_vector[cs->exception_index]);
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env->exception_taken = 1;
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} else {
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qemu_log("%s(pc = %08x) bad exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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qemu_log_mask(CPU_LOG_INT, "%s(pc = %08x) bad exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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}
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break;
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@ -245,8 +245,8 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
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{
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int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
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if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
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pc, env->sregs[PS]);
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qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x), PS = %08x\n",
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pc, env->sregs[PS]);
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HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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uint32_t windowstart = xtensa_replicate_windowstart(env) >>
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@ -307,9 +307,9 @@ uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
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if (n == 0 || (m != 0 && m != n) ||
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((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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qemu_log("Illegal retw instruction(pc = %08x), "
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"PS = %08x, m = %d, n = %d\n",
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pc, env->sregs[PS], m, n);
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qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x), "
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"PS = %08x, m = %d, n = %d\n",
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pc, env->sregs[PS], m, n);
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HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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int owb = windowbase;
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@ -743,8 +743,8 @@ void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
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xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
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tlb_flush_page(cs, entry->vaddr);
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} else {
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qemu_log("%s %d, %d, %d trying to set immutable entry\n",
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__func__, dtlb, wi, ei);
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qemu_log_mask(LOG_GUEST_ERROR, "%s %d, %d, %d trying to set immutable entry\n",
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__func__, dtlb, wi, ei);
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}
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} else {
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tlb_flush_page(cs, entry->vaddr);
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@ -806,15 +806,15 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
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}
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/* contiguous mask after inversion is one less than some power of 2 */
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if ((~mask + 1) & ~mask) {
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qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
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qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
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/* cut mask after the first zero bit */
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mask = 0xffffffff << (32 - clo32(mask));
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}
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if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
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flags, &env->cpu_watchpoint[i])) {
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env->cpu_watchpoint[i] = NULL;
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qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
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dbreaka & mask, ~mask + 1);
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qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0x%08x/%d\n",
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dbreaka & mask, ~mask + 1);
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}
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}
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@ -501,9 +501,9 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
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{
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if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
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if (sregnames[sr].name) {
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qemu_log("SR %s is not configured\n", sregnames[sr].name);
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qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
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} else {
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qemu_log("SR %d is not implemented\n", sr);
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qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
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}
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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return false;
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@ -514,8 +514,8 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
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[SR_X] = "xsr",
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};
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assert(access < ARRAY_SIZE(access_text) && access_text[access]);
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qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
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access_text[access]);
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qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
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access_text[access]);
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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return false;
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}
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@ -875,18 +875,18 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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{
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#define HAS_OPTION_BITS(opt) do { \
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if (!option_bits_enabled(dc, opt)) { \
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qemu_log("Option is not enabled %s:%d\n", \
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__FILE__, __LINE__); \
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qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
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__FILE__, __LINE__); \
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goto invalid_opcode; \
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} \
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} while (0)
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#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
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#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
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#define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
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#define RESERVED() do { \
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qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
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dc->pc, b0, b1, b2, __FILE__, __LINE__); \
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qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
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dc->pc, b0, b1, b2, __FILE__, __LINE__); \
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goto invalid_opcode; \
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} while (0)
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@ -1186,7 +1186,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
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}
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} else {
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qemu_log("RFI %d is illegal\n", RRR_S);
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qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S);
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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}
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break;
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@ -1222,7 +1222,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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gen_helper_simcall(cpu_env);
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}
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} else {
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qemu_log("SIMCALL but semihosting is disabled\n");
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qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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}
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break;
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@ -1865,7 +1865,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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if (uregnames[st].name) {
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tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
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} else {
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qemu_log("RUR %d not implemented, ", st);
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qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st);
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TBD();
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}
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}
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@ -1876,7 +1876,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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if (uregnames[RSR_SR].name) {
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gen_wur(RSR_SR, cpu_R[RRR_T]);
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} else {
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qemu_log("WUR %d not implemented, ", RSR_SR);
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qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR);
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TBD();
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}
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}
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@ -3006,7 +3006,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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return;
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invalid_opcode:
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qemu_log("INVALID(pc = %08x)\n", dc->pc);
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qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc);
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gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
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#undef HAS_OPTION
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}
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@ -313,7 +313,7 @@ void HELPER(simcall)(CPUXtensaState *env)
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break;
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default:
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qemu_log("%s(%d): not implemented\n", __func__, regs[2]);
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qemu_log_mask(LOG_GUEST_ERROR, "%s(%d): not implemented\n", __func__, regs[2]);
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regs[2] = -1;
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regs[3] = TARGET_ENOSYS;
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break;
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