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target-sparc: Use DisasCompare and movcond in MOVR

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Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2012-10-05 16:55:01 -07:00 committed by Blue Swirl
parent f52879b441
commit c33f80f52a
1 changed files with 14 additions and 17 deletions
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31
target-sparc/translate.c
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@ -4118,27 +4118,24 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x2f: /* V9 movr */ case 0x2f: /* V9 movr */
{ {
int cond = GET_FIELD_SP(insn, 10, 12); int cond = GET_FIELD_SP(insn, 10, 12);
int l1; DisasCompare cmp;
cpu_src1 = get_src1(insn, cpu_src1); gen_compare_reg(&cmp, cond, cpu_src1);
l1 = gen_new_label();
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
cpu_src1, 0, l1);
if (IS_IMM) { /* immediate */
TCGv r_const;
/* The get_src2 above loaded the normal 13-bit
immediate field, not the 10-bit field we have
in movr. But it did handle the reg case. */
if (IS_IMM) {
simm = GET_FIELD_SPs(insn, 0, 9); simm = GET_FIELD_SPs(insn, 0, 9);
r_const = tcg_const_tl(simm); tcg_gen_movi_tl(cpu_src2, simm);
gen_movl_TN_reg(rd, r_const);
tcg_temp_free(r_const);
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
gen_movl_reg_TN(rs2, cpu_tmp0);
gen_movl_TN_reg(rd, cpu_tmp0);
} }
gen_set_label(l1);
gen_movl_reg_TN(rd, cpu_dst);
tcg_gen_movcond_tl(cmp.cond, cpu_dst,
cmp.c1, cmp.c2,
cpu_src2, cpu_dst);
free_compare(&cmp);
gen_movl_TN_reg(rd, cpu_dst);
break; break;
} }
#endif #endif