target/ppc: fix PMU Group A register read/write exceptions
A call to "gen_(hv)priv_exception" should use POWERPC_EXCP_PRIV_* as the
'error' argument instead of POWERPC_EXCP_INVAL_*, and POWERPC_EXCP_FU is
an exception type, not an exception error code. To correctly set
FSCR[IC], we should raise Facility Unavailable with this exception type
and IC value as the error code.
Fixes: 565cb10967
("target/ppc: add user read/write functions for MMCR0")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220627141104.669152-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
parent
e898517985
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c35553b5e7
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@ -22,7 +22,7 @@
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static bool spr_groupA_read_allowed(DisasContext *ctx)
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{
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if (!ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
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gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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return false;
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}
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@ -46,10 +46,10 @@ static bool spr_groupA_write_allowed(DisasContext *ctx)
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if (ctx->mmcr0_pmcc1) {
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/* PMCC = 0b01 */
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gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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} else {
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/* PMCC = 0b00 */
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gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
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gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
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}
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return false;
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@ -214,7 +214,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
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* Interrupt.
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*/
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if (ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
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gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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return;
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}
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@ -249,7 +249,7 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
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* Interrupt.
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*/
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if (ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
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gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
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gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
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return;
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}
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