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target/i386: Support Arch LBR in CPUID enumeration

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If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).

Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-9-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Yang Weijiang 2022-02-15 14:52:58 -05:00 committed by Paolo Bonzini
parent d19d6ffa07
commit c3c67679f6
1 changed files with 19 additions and 1 deletions
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20
target/i386/cpu.c
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@ -855,7 +855,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"fsrm", NULL, NULL, NULL, "fsrm", NULL, NULL, NULL,
"avx512-vp2intersect", NULL, "md-clear", NULL, "avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, "serialize", NULL, NULL, NULL, "serialize", NULL,
"tsx-ldtrk", NULL, NULL /* pconfig */, NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
NULL, NULL, "amx-bf16", "avx512-fp16", NULL, NULL, "amx-bf16", "avx512-fp16",
"amx-tile", "amx-int8", "spec-ctrl", "stibp", "amx-tile", "amx-int8", "spec-ctrl", "stibp",
NULL, "arch-capabilities", "core-capability", "ssbd", NULL, "arch-capabilities", "core-capability", "ssbd",
@ -5420,6 +5420,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
assert(!(*eax & ~0x1f)); assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */ *ebx &= 0xffff; /* The count doesn't need to be reliable. */
break; break;
case 0x1C:
if (accel_uses_host_cpuid() && cpu->enable_pmu &&
(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
*edx = 0;
}
break;
case 0x1F: case 0x1F:
/* V2 Extended Topology Enumeration Leaf */ /* V2 Extended Topology Enumeration Leaf */
if (env->nr_dies < 2) { if (env->nr_dies < 2) {
@ -5482,6 +5489,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ebx = xsave_area_size(xstate, true); *ebx = xsave_area_size(xstate, true);
*ecx = env->features[FEAT_XSAVE_XSS_LO]; *ecx = env->features[FEAT_XSAVE_XSS_LO];
*edx = env->features[FEAT_XSAVE_XSS_HI]; *edx = env->features[FEAT_XSAVE_XSS_HI];
if (kvm_enabled() && cpu->enable_pmu &&
(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) &&
(*eax & CPUID_XSAVE_XSAVES)) {
*ecx |= XSTATE_ARCH_LBR_MASK;
} else {
*ecx &= ~XSTATE_ARCH_LBR_MASK;
}
} else if (count == 0xf &&
accel_uses_host_cpuid() && cpu->enable_pmu &&
(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx);
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) { } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
const ExtSaveArea *esa = &x86_ext_save_areas[count]; const ExtSaveArea *esa = &x86_ext_save_areas[count];