target/ppc: Clear fpstatus flags on helpers missing it
In ppc emulation, exception flags are not cleared at the end of an instruction. Instead, the next instruction is responsible to clear it before its emulation. However, some helpers are not doing it, causing an issue where the previously set exception flags are being used and leading to incorrect values being set in FPSCR. Fix this by clearing fp_status before doing the instruction 'real' work for the following helpers that were missing this behavior: - VSX_CVT_INT_TO_FP_VECTOR - VSX_CVT_FP_TO_FP - VSX_CVT_FP_TO_INT_VECTOR - VSX_CVT_FP_TO_INT2 - VSX_CVT_FP_TO_INT - VSX_CVT_FP_TO_FP_HP - VSX_CVT_FP_TO_FP_VECTOR - VSX_CMP - VSX_ROUND - xscvqpdp - xscvdpsp[n] Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-9-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Víctor Colombo
Daniel Henrique Barboza
parent
4b65b6e769
commit
c3f24257e3
@ -2628,6 +2628,8 @@ uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
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int all_true = 1; \
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int all_false = 1; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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if (unlikely(tp##_is_any_nan(xa->fld) || \
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tp##_is_any_nan(xb->fld))) { \
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@ -2681,6 +2683,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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ppc_vsr_t t = { }; \
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int i; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
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if (unlikely(stp##_is_signaling_nan(xb->sfld, \
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@ -2706,6 +2710,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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ppc_vsr_t t = { }; \
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int i; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
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if (unlikely(stp##_is_signaling_nan(xb->VsrD(i), \
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@ -2743,6 +2749,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \
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ppc_vsr_t t = *xt; \
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int i; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
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if (unlikely(stp##_is_signaling_nan(xb->sfld, \
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@ -2778,6 +2786,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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ppc_vsr_t t = { }; \
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int i; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
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if (unlikely(stp##_is_signaling_nan(xb->sfld, \
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@ -2825,6 +2835,8 @@ void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
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ppc_vsr_t t = { };
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float_status tstat;
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helper_reset_fpstatus(env);
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tstat = env->fp_status;
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if (ro != 0) {
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tstat.float_rounding_mode = float_round_to_odd;
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@ -2846,6 +2858,7 @@ uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
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{
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uint64_t result, sign, exp, frac;
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helper_reset_fpstatus(env);
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float_status tstat = env->fp_status;
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set_float_exception_flags(0, &tstat);
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@ -2901,22 +2914,20 @@ uint64_t helper_XSCVSPDPN(uint64_t xb)
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#define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, sfi, rnan) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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{ \
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int all_flags = env->fp_status.float_exception_flags, flags; \
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ppc_vsr_t t = { }; \
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int i; \
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int i, flags; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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env->fp_status.float_exception_flags = 0; \
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t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
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flags = env->fp_status.float_exception_flags; \
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if (unlikely(flags & float_flag_invalid)) { \
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t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
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} \
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all_flags |= flags; \
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} \
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\
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*xt = t; \
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env->fp_status.float_exception_flags = all_flags; \
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do_float_check_status(env, sfi, GETPC()); \
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}
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@ -2968,12 +2979,12 @@ VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000000000000000ULL);
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#define VSX_CVT_FP_TO_INT2(op, nels, stp, ttp, sfi, rnan) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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{ \
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int all_flags = env->fp_status.float_exception_flags, flags; \
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ppc_vsr_t t = { }; \
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int i; \
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int i, flags; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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env->fp_status.float_exception_flags = 0; \
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t.VsrW(2 * i) = stp##_to_##ttp##_round_to_zero(xb->VsrD(i), \
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&env->fp_status); \
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flags = env->fp_status.float_exception_flags; \
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@ -2982,11 +2993,9 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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rnan, 0, GETPC()); \
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} \
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t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
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all_flags |= flags; \
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} \
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\
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*xt = t; \
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env->fp_status.float_exception_flags = all_flags; \
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do_float_check_status(env, sfi, GETPC()); \
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}
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@ -3011,6 +3020,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \
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ppc_vsr_t t = { }; \
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int flags; \
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\
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helper_reset_fpstatus(env); \
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\
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t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
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flags = get_float_exception_flags(&env->fp_status); \
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if (flags & float_flag_invalid) { \
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@ -3023,7 +3034,6 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \
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VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
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0x8000000000000000ULL)
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VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
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0xffffffff80000000ULL)
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VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
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@ -3046,6 +3056,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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ppc_vsr_t t = { }; \
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int i; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
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if (r2sp) { \
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@ -3115,6 +3127,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \
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{ \
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ppc_vsr_t t = *xt; \
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\
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helper_reset_fpstatus(env); \
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t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
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helper_compute_fprf_##ttp(env, t.tfld); \
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\
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@ -3148,6 +3161,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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int i; \
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FloatRoundMode curr_rounding_mode; \
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\
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helper_reset_fpstatus(env); \
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\
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if (rmode != FLOAT_ROUND_CURRENT) { \
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curr_rounding_mode = get_float_rounding_mode(&env->fp_status); \
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set_float_rounding_mode(rmode, &env->fp_status); \
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